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[Qemu-devel] [PULL 25/66] ppc: Don't update the NIP in floating point ge
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From: |
David Gibson |
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Subject: |
[Qemu-devel] [PULL 25/66] ppc: Don't update the NIP in floating point generated code |
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Date: |
Tue, 6 Sep 2016 13:40:12 +1000 |
From: Benjamin Herrenschmidt <address@hidden>
This is no longer necessary as the helpers will properly retrieve
the return address.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/translate/fp-impl.c | 28 ----------------------------
target-ppc/translate/vsx-impl.c | 6 ------
2 files changed, 34 deletions(-)
diff --git a/target-ppc/translate/fp-impl.c b/target-ppc/translate/fp-impl.c
index 2abc386..9ba9289 100644
--- a/target-ppc/translate/fp-impl.c
+++ b/target-ppc/translate/fp-impl.c
@@ -38,8 +38,6 @@ static void gen_f##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- /* NIP cannot be restored if the memory exception comes from an helper */ \
- gen_update_nip(ctx, ctx->nip - 4); \
gen_reset_fpstatus(); \
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rA(ctx->opcode)], \
@@ -67,8 +65,6 @@ static void gen_f##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- /* NIP cannot be restored if the memory exception comes from an helper */ \
- gen_update_nip(ctx, ctx->nip - 4); \
gen_reset_fpstatus(); \
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rA(ctx->opcode)], \
@@ -95,8 +91,6 @@ static void gen_f##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- /* NIP cannot be restored if the memory exception comes from an helper */ \
- gen_update_nip(ctx, ctx->nip - 4); \
gen_reset_fpstatus(); \
gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rA(ctx->opcode)], \
@@ -123,8 +117,6 @@ static void gen_f##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- /* NIP cannot be restored if the memory exception comes from an helper */ \
- gen_update_nip(ctx, ctx->nip - 4); \
gen_reset_fpstatus(); \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
@@ -143,8 +135,6 @@ static void gen_f##name(DisasContext *ctx)
\
gen_exception(ctx, POWERPC_EXCP_FPU); \
return; \
} \
- /* NIP cannot be restored if the memory exception comes from an helper */ \
- gen_update_nip(ctx, ctx->nip - 4); \
gen_reset_fpstatus(); \
gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
cpu_fpr[rB(ctx->opcode)]); \
@@ -179,8 +169,6 @@ static void gen_frsqrtes(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
gen_reset_fpstatus();
gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rB(ctx->opcode)]);
@@ -205,8 +193,6 @@ static void gen_fsqrt(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
gen_reset_fpstatus();
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rB(ctx->opcode)]);
@@ -222,8 +208,6 @@ static void gen_fsqrts(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
gen_reset_fpstatus();
gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
cpu_fpr[rB(ctx->opcode)]);
@@ -313,8 +297,6 @@ static void gen_fcmpo(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
gen_reset_fpstatus();
crf = tcg_const_i32(crfD(ctx->opcode));
gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
@@ -331,8 +313,6 @@ static void gen_fcmpu(DisasContext *ctx)
gen_exception(ctx, POWERPC_EXCP_FPU);
return;
}
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
gen_reset_fpstatus();
crf = tcg_const_i32(crfD(ctx->opcode));
gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
@@ -502,8 +482,6 @@ static void gen_mtfsb0(DisasContext *ctx)
gen_reset_fpstatus();
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
TCGv_i32 t0;
- /* NIP cannot be restored if the memory exception comes from an helper
*/
- gen_update_nip(ctx, ctx->nip - 4);
t0 = tcg_const_i32(crb);
gen_helper_fpscr_clrbit(cpu_env, t0);
tcg_temp_free_i32(t0);
@@ -528,8 +506,6 @@ static void gen_mtfsb1(DisasContext *ctx)
/* XXX: we pretend we can only do IEEE floating-point computations */
if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
TCGv_i32 t0;
- /* NIP cannot be restored if the memory exception comes from an helper
*/
- gen_update_nip(ctx, ctx->nip - 4);
t0 = tcg_const_i32(crb);
gen_helper_fpscr_setbit(cpu_env, t0);
tcg_temp_free_i32(t0);
@@ -559,8 +535,6 @@ static void gen_mtfsf(DisasContext *ctx)
gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
return;
}
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
gen_reset_fpstatus();
if (l) {
t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
@@ -595,8 +569,6 @@ static void gen_mtfsfi(DisasContext *ctx)
return;
}
sh = (8 * w) + 7 - bf;
- /* NIP cannot be restored if the memory exception comes from an helper */
- gen_update_nip(ctx, ctx->nip - 4);
gen_reset_fpstatus();
t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
t1 = tcg_const_i32(1 << sh);
diff --git a/target-ppc/translate/vsx-impl.c b/target-ppc/translate/vsx-impl.c
index 7361c47..9f77b06 100644
--- a/target-ppc/translate/vsx-impl.c
+++ b/target-ppc/translate/vsx-impl.c
@@ -380,8 +380,6 @@ static void gen_##name(DisasContext * ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- /* NIP cannot be restored if the memory exception comes from an helper */ \
- gen_update_nip(ctx, ctx->nip - 4); \
opc = tcg_const_i32(ctx->opcode); \
gen_helper_##name(cpu_env, opc); \
tcg_temp_free_i32(opc); \
@@ -394,10 +392,6 @@ static void gen_##name(DisasContext * ctx)
\
gen_exception(ctx, POWERPC_EXCP_VSXU); \
return; \
} \
- /* NIP cannot be restored if the exception comes */ \
- /* from a helper. */ \
- gen_update_nip(ctx, ctx->nip - 4); \
- \
gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
cpu_vsrh(xB(ctx->opcode))); \
}
--
2.7.4
- [Qemu-devel] [PULL 34/66] ppc: Don't update NIP BookE 2.06 tlbwe, (continued)
- [Qemu-devel] [PULL 34/66] ppc: Don't update NIP BookE 2.06 tlbwe, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 24/66] ppc: Make float_check_status() pass the return address, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 36/66] ppc: Don't update NIP if not taking alignment exceptions, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 31/66] ppc: Fix source NIP on SLB related interrupts, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 23/66] ppc: Make float_invalid_op_excp() pass the return address, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 28/66] ppc: Don't update NIP in lmw/stmw/icbi, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 38/66] ppc: Make alignment exceptions suck less, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 19/66] ppc: Move DFP ops out of translate.c, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 03/66] target-ppc: Introduce Power9 family, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 26/66] ppc: FP exceptions are always precise, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 25/66] ppc: Don't update the NIP in floating point generated code,
David Gibson <=
- [Qemu-devel] [PULL 45/66] ppc: Speed up load/store multiple, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 60/66] ppc: Don't generate dead code on unconditional branches, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 42/66] ppc: Don't set access_type on all load/stores on hash64, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 49/66] target-ppc: add vabsdu[b, h, w] instructions, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 46/66] target-ppc: implement branch-less divw[o][.], David Gibson, 2016/09/05
- [Qemu-devel] [PULL 32/66] ppc: Don't update NIP in DCR access routines, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 51/66] target-ppc: add vslv instruction, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 43/66] ppc: Use a helper to generate "LE unsupported" alignment interrupts, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 41/66] ppc: Fix CFAR updates, David Gibson, 2016/09/05
- [Qemu-devel] [PULL 48/66] target-ppc: add dtstsfi[q] instructions, David Gibson, 2016/09/05