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[Qemu-devel] [PATCH 4/7] target-mips: Provide function to test if a CPU
From: |
Paul Burton |
Subject: |
[Qemu-devel] [PATCH 4/7] target-mips: Provide function to test if a CPU supports an ISA |
Date: |
Fri, 19 Aug 2016 20:09:00 +0100 |
Provide a new cpu_supports_isa function which allows callers to
determine whether a CPU supports one of the ISA_ flags, by testing
whether the associated struct mips_def_t sets the ISA flags in its
insn_flags field.
An example use of this is to allow boards which generate bootloader code
to determine the properties of the CPU that will be used, for example
whether the CPU is 64 bit or which architecture revision it implements.
Signed-off-by: Paul Burton <address@hidden>
---
target-mips/cpu.h | 1 +
target-mips/translate.c | 10 ++++++++++
2 files changed, 11 insertions(+)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 5182dc7..cbd17df 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -812,6 +812,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo,
void *puc);
#define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
bool cpu_supports_cps_smp(const char *cpu_model);
+bool cpu_supports_isa(const char *cpu_model, unsigned int isa);
void cpu_set_exception_base(int vp_index, target_ulong address);
/* TODO QOM'ify CPU reset and remove */
diff --git a/target-mips/translate.c b/target-mips/translate.c
index bab52cb..c212e4f 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20192,6 +20192,16 @@ bool cpu_supports_cps_smp(const char *cpu_model)
return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
+bool cpu_supports_isa(const char *cpu_model, unsigned int isa)
+{
+ const mips_def_t *def = cpu_mips_find_by_name(cpu_model);
+ if (!def) {
+ return false;
+ }
+
+ return (def->insn_flags & isa) != 0;
+}
+
void cpu_set_exception_base(int vp_index, target_ulong address)
{
MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
--
2.9.3
- [Qemu-devel] [PATCH 0/7] MIPS Boston board support, Paul Burton, 2016/08/19
- [Qemu-devel] [PATCH 1/7] hw/mips_cmgcr: allow GCR base to be moved, Paul Burton, 2016/08/19
- [Qemu-devel] [PATCH 2/7] hw/mips_gictimer: provide API for retrieving frequency, Paul Burton, 2016/08/19
- [Qemu-devel] [PATCH 3/7] hw/mips_gic: Update pin state on mask changes, Paul Burton, 2016/08/19
- [Qemu-devel] [PATCH 4/7] target-mips: Provide function to test if a CPU supports an ISA,
Paul Burton <=
- [Qemu-devel] [PATCH 5/7] loader: Support Flattened Image Trees (FIT images), Paul Burton, 2016/08/19
- [Qemu-devel] [PATCH 6/7] hw: xilinx-pcie: Add support for Xilinx AXI PCIe Controller, Paul Burton, 2016/08/19
- [Qemu-devel] [PATCH 7/7] hw/mips: MIPS Boston board support, Paul Burton, 2016/08/19
- Re: [Qemu-devel] [PATCH 0/7] MIPS Boston board support, no-reply, 2016/08/19