Re: [Qemu-devel] target-ppc: SPR_BOOKE_ESR not set on FP exceptions

[David Gibson]

On Fri, Jul 29, 2016 at 08:04:04AM -0500, address@hidden wrote:
> David Gibson <address@hidden> wrote on 07/29/2016 12:40:15 
> AM:
> 
> > From: David Gibson <address@hidden>
> > To: address@hidden
> > Cc: address@hidden, address@hidden, address@hidden
> > Date: 07/29/2016 12:38 AM
> > Subject: Re: target-ppc: SPR_BOOKE_ESR not set on FP exceptions
> > 
> > On Thu, Jul 28, 2016 at 06:32:27PM -0500, address@hidden wrote:
> ...
> > > I did a quick check of the bits set in the POWERPC_EXCP_PROGRAM case.
> > > The classic PPC sets SRR1 bits 11--15 depending on the exception.  In
> > > Book E these correspond to bits 43--47,
> > 
> > Um.. what?  I'm not understanding where this bit shift is coming
> > from. 
> 
> Sorry, I was looking at an old "classic" 32-bit manual for the SRR1 
> exception definition and a 64-bit manual for the BookE.  They are
> the same bits.  MSB0 bit numbering bytes again :-)

Ok.  Can you re-do your analysis and submit a patch to fix this?

-- 
David Gibson                    | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au  | minimalist, thank you.  NOT _the_ _other_
                                | _way_ _around_!
http://www.ozlabs.org/~dgibson

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