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[Qemu-devel] [PATCH 0/6] arm: add ast2500 support

From: Cédric Le Goater
Subject: [Qemu-devel] [PATCH 0/6] arm: add ast2500 support
Date: Wed, 27 Jul 2016 18:46:52 +0200

The ast2500 soc being very close to the ast2400 soc, the goal of the
changes below is to modify the existing platform 'palmetto-bmc' and
existing soc 'ast2400' to take into account the small differences and
avoid code duplication. This is mostly inspired by the realview

First patches rework the palmetto-bmc platform and the ast2400 soc
models to provide room to other platforms and socs which have a common
design. Being able to set the 'silicon-rev' and the cpu model are the
primary motivation.

I tried to link all the silicon-rev properties to a common one (in the
SCU controller) but I failed to find the right pattern. I am not sure
it is possible to have multiple aliases on the same property. You will
see what I came up with in the first patch.

The last patches add support for the new ast2500 soc in the required
controller (sdmc and scu) and define a new platform for an Aspeed
evaluation board.

The 'palmetto-bmc.c' file could be renamed to 'aspeed.c' now that it
contains more than one platform, but I don't really like the idea as
it breaks history. As for the ast2400.c file, I think we are fine as
we are just adding a configurable cpu. Nothing major. Please advise on
that topic.

On the ast2500, I am still having a little issue under uboot which
sets the vbar doing :

        mcr     p15, 0, r0, c12, c0, 0  /* Set VBAR */

and this is trapped as an undefined instruction by qemu.

Looking at hw/arm/helper.c, the VBAR register seems to be defined only
for feature ARM_FEATURE_V7 (v7_cp_reginfo). The ast2500 soc uses a
arm1176 which defines ARM_FEATURE_EL3 which gives us a VBAR_EL3.
According to th specs, the arm1176jzf-s has a Vector Base Address
Register. So am I missing something in the board definition or is
uboot being too optimistic on the cpu features ? This is confusing for
me, some direction would be welcomed :)

A part from that, the soc behaves fine.


Cédric Le Goater (6):
  palmetto-bmc: add a "silicon-rev" property at the soc level
  palmetto-bmc: replace palmetto_bmc with aspeed
  ast2400: use machine cpu_model to initialize the soc cpu
  palmetto-bmc: add board specific configuration
  aspeed/scu: add ast2500 support
  arm: add support for an ast2500 evaluation board

 hw/arm/ast2400.c             |  26 +++++++---
 hw/arm/palmetto-bmc.c        | 115 ++++++++++++++++++++++++++++++++++---------
 hw/misc/aspeed_scu.c         |  45 ++++++++++++++++-
 hw/misc/aspeed_sdmc.c        |   1 +
 include/hw/arm/ast2400.h     |   5 ++
 include/hw/misc/aspeed_scu.h |   1 +
 6 files changed, 163 insertions(+), 30 deletions(-)


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