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[Qemu-devel] [PATCHv2 23/31] ppc: Make alignment exceptions suck less
From: |
Benjamin Herrenschmidt |
Subject: |
[Qemu-devel] [PATCHv2 23/31] ppc: Make alignment exceptions suck less |
Date: |
Wed, 27 Jul 2016 16:56:41 +1000 |
The current alignment exception generation tries to load the opcode
to put in DSISR from a context where a cpu_ldl_code() is really not
a good idea. It might fault and longjmp out and that's not something
we want happening here.
Instead, pass the releavant opcode bits via the error_code.
There are a couple of cases of alignment interrupts that won't set
anything, the ones coming from access to direct store segments, but
that doesn't happen in practice, nobody used direct store segments
and they are gone from newer chips.
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
---
target-ppc/excp_helper.c | 9 +++++----
target-ppc/translate.c | 2 +-
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index 882d529..04ed4da 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -260,11 +260,12 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
}
break;
case POWERPC_EXCP_ALIGN: /* Alignment exception */
- /* XXX: this is false */
/* Get rS/rD and rA from faulting opcode */
- /* Broken for LE mode */
- env->spr[SPR_DSISR] |= (cpu_ldl_code(env, env->nip)
- & 0x03FF0000) >> 16;
+ /* Note: the opcode fields will not be set properly for a direct
+ * store load/store, but nobody cares as nobody actually uses
+ * direct store segments.
+ */
+ env->spr[SPR_DSISR] |= (env->error_code & 0x03FF0000) >> 16;
break;
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 5c68b1d..20c9cbb 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -2416,7 +2416,7 @@ static inline void gen_check_align(DisasContext *ctx,
TCGv EA, int mask)
tcg_gen_andi_tl(t0, EA, mask);
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
- t2 = tcg_const_i32(0);
+ t2 = tcg_const_i32(ctx->opcode & 0x03FF0000);
gen_update_nip(ctx, ctx->nip - 4);
gen_helper_raise_exception_err(cpu_env, t1, t2);
tcg_temp_free_i32(t1);
--
2.7.4
- [Qemu-devel] [PATCHv2 13/31] ppc: Don't update NIP in lmw/stmw/icbi, (continued)
- [Qemu-devel] [PATCHv2 13/31] ppc: Don't update NIP in lmw/stmw/icbi, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 14/31] ppc: Make tlb_fill() use new exception helper, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 15/31] ppc: Rework NIP updates vs. exception generation, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 16/31] ppc: Fix source NIP on SLB related interrupts, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 17/31] ppc: Don't update NIP in DCR access routines, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 22/31] ppc: Don't update NIP in dcbz and lscbx, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 21/31] ppc: Don't update NIP if not taking alignment exceptions, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 18/31] ppc: Don't update NIP in facility unavailable interrupts, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 19/31] ppc: Don't update NIP BookE 2.06 tlbwe, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 20/31] ppc: Don't update NIP on conditional trap instructions, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 23/31] ppc: Make alignment exceptions suck less,
Benjamin Herrenschmidt <=
- [Qemu-devel] [PATCHv2 24/31] ppc: Handle unconditional (always/never) traps at translation time, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 27/31] ppc: Avoid double translation for lvx/lvxl/stvx/stvxl, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 25/31] ppc: Speed up dcbz, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 26/31] ppc: Fix CFAR updates, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 29/31] ppc: Use a helper to generate "LE unsupported" alignment interrupts, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 28/31] ppc: Don't set access_type on all load/stores on hash64, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 30/31] ppc: load/store multiple and string insns don't do LE, Benjamin Herrenschmidt, 2016/07/27
- [Qemu-devel] [PATCHv2 31/31] ppc: Speed up load/store multiple, Benjamin Herrenschmidt, 2016/07/27