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[Qemu-devel] [PULL 05/11] hw/arm/virt: tcg: adjust MPIDR like KVM
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 05/11] hw/arm/virt: tcg: adjust MPIDR like KVM |
Date: |
Thu, 14 Jul 2016 17:29:37 +0100 |
From: Andrew Jones <address@hidden>
KVM adjusts the MPIDR of guest vcpus based on the architecture of
the host, 32-bit vs. 64-bit, and, for 64-bit, also on the type of
GIC the guest is using. To be consistent and improve SGI efficiency
we make the same adjustments for TCG as 64-bit KVM hosts. We neglect
to add consistency with 32-bit KVM hosts, as that would reduce SGI
efficiency and KVM is expected to change.
As MPIDR is a system register, and thus guest visible, we only make
adjustments for current and later versioned machines.
Signed-off-by: Andrew Jones <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/arm/virt.c | 25 ++++++++++++++++++++++++-
1 file changed, 24 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 4dafd42..a193b5a 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -52,7 +52,8 @@
#include "hw/arm/sysbus-fdt.h"
#include "hw/platform-bus.h"
#include "hw/arm/fdt.h"
-#include "hw/intc/arm_gic_common.h"
+#include "hw/intc/arm_gic.h"
+#include "hw/intc/arm_gicv3_common.h"
#include "kvm_arm.h"
#include "hw/smbios/smbios.h"
#include "qapi/visitor.h"
@@ -82,6 +83,7 @@ typedef struct VirtBoardInfo {
typedef struct {
MachineClass parent;
VirtBoardInfo *daughterboard;
+ bool disallow_affinity_adjustment;
} VirtMachineClass;
typedef struct {
@@ -1165,6 +1167,7 @@ void virt_guest_info_machine_done(Notifier *notifier,
void *data)
static void machvirt_init(MachineState *machine)
{
VirtMachineState *vms = VIRT_MACHINE(machine);
+ VirtMachineClass *vmc = VIRT_MACHINE_GET_CLASS(machine);
qemu_irq pic[NUM_IRQS];
MemoryRegion *sysmem = get_system_memory();
MemoryRegion *secure_sysmem = NULL;
@@ -1181,6 +1184,7 @@ static void machvirt_init(MachineState *machine)
CPUClass *cc;
Error *err = NULL;
bool firmware_loaded = bios_name || drive_get(IF_PFLASH, 0, 0);
+ uint8_t clustersz;
if (!cpu_model) {
cpu_model = "cortex-a15";
@@ -1226,8 +1230,10 @@ static void machvirt_init(MachineState *machine)
*/
if (gic_version == 3) {
virt_max_cpus = vbi->memmap[VIRT_GIC_REDIST].size / 0x20000;
+ clustersz = GICV3_TARGETLIST_BITS;
} else {
virt_max_cpus = GIC_NCPU;
+ clustersz = GIC_TARGETLIST_BITS;
}
if (max_cpus > virt_max_cpus) {
@@ -1281,6 +1287,20 @@ static void machvirt_init(MachineState *machine)
for (n = 0; n < smp_cpus; n++) {
Object *cpuobj = object_new(typename);
+ if (!vmc->disallow_affinity_adjustment) {
+ /* Adjust MPIDR like 64-bit KVM hosts, which incorporate the
+ * GIC's target-list limitations. 32-bit KVM hosts currently
+ * always create clusters of 4 CPUs, but that is expected to
+ * change when they gain support for gicv3. When KVM is enabled
+ * it will override the changes we make here, therefore our
+ * purposes are to make TCG consistent (with 64-bit KVM hosts)
+ * and to improve SGI efficiency.
+ */
+ uint8_t aff1 = n / clustersz;
+ uint8_t aff0 = n % clustersz;
+ object_property_set_int(cpuobj, (aff1 << ARM_AFF1_SHIFT) | aff0,
+ "mp-affinity", NULL);
+ }
if (!vms->secure) {
object_property_set_bool(cpuobj, false, "has_el3", NULL);
@@ -1507,7 +1527,10 @@ static void virt_2_6_instance_init(Object *obj)
static void virt_machine_2_6_options(MachineClass *mc)
{
+ VirtMachineClass *vmc = VIRT_MACHINE_CLASS(OBJECT_CLASS(mc));
+
virt_machine_2_7_options(mc);
SET_MACHINE_COMPAT(mc, VIRT_COMPAT_2_6);
+ vmc->disallow_affinity_adjustment = true;
}
DEFINE_VIRT_MACHINE(2, 6)
--
1.9.1
- [Qemu-devel] [PULL 00/11] target-arm queue, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 10/11] ast2400: pretend DMAs are done for U-boot, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 11/11] ast2400: externalize revision numbers, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 09/11] ast2400: replace aspeed_smc_is_implemented(), Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 08/11] hw/misc: fix typo in Aspeed SCU hw-strap2 property name, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 04/11] gic: provide defines for v2/v3 targetlist sizes, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 07/11] m25p80: Fix QIOR/DIOR handling for Winbond, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 05/11] hw/arm/virt: tcg: adjust MPIDR like KVM,
Peter Maydell <=
- [Qemu-devel] [PULL 06/11] target-arm: Add missed AArch32 TLBI sytem registers, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 03/11] target-arm: Use Neon for zero checking, Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 02/11] Revert "hw/ptimer: Perform counter wrap around if timer already expired", Peter Maydell, 2016/07/14
- [Qemu-devel] [PULL 01/11] virtio-mmio: format transport base address in BusClass.get_dev_path, Peter Maydell, 2016/07/14
- Re: [Qemu-devel] [PULL 00/11] target-arm queue, Peter Maydell, 2016/07/14