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[Qemu-devel] [PULL 04/11] target-mips: add exception base to MIPS CPU
From: |
Leon Alrae |
Subject: |
[Qemu-devel] [PULL 04/11] target-mips: add exception base to MIPS CPU |
Date: |
Tue, 12 Jul 2016 12:14:50 +0100 |
Replace hardcoded 0xbfc00000 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.
Signed-off-by: Leon Alrae <address@hidden>
---
target-mips/cpu.h | 2 ++
target-mips/helper.c | 6 +++---
target-mips/translate.c | 9 ++++++++-
3 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 1037f9b..fe1c4b8 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -616,6 +616,7 @@ struct CPUMIPSState {
void *irq[8];
QEMUTimer *timer; /* Internal timer */
MemoryRegion *itc_tag; /* ITC Configuration Tags */
+ target_ulong exception_base; /* ExceptionBase input to the core */
};
/**
@@ -807,6 +808,7 @@ int cpu_mips_signal_handler(int host_signum, void *pinfo,
void *puc);
#define cpu_init(cpu_model) CPU(cpu_mips_init(cpu_model))
bool cpu_supports_cps_smp(const char *cpu_model);
+void cpu_set_exception_base(int vp_index, target_ulong address);
/* TODO QOM'ify CPU reset and remove */
void cpu_state_reset(CPUMIPSState *s);
diff --git a/target-mips/helper.c b/target-mips/helper.c
index 65fbef0..1402ff0 100644
--- a/target-mips/helper.c
+++ b/target-mips/helper.c
@@ -640,7 +640,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1U << CP0Ca_BD);
- env->active_tc.PC = (int32_t)0xBFC00480;
+ env->active_tc.PC = env->exception_base + 0x480;
set_hflags_for_handler(env);
break;
case EXCP_RESET:
@@ -667,7 +667,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags &= ~(MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1U << CP0Ca_BD);
- env->active_tc.PC = (int32_t)0xBFC00000;
+ env->active_tc.PC = env->exception_base;
set_hflags_for_handler(env);
break;
case EXCP_EXT_INTERRUPT:
@@ -849,7 +849,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
}
env->hflags &= ~MIPS_HFLAG_BMASK;
if (env->CP0_Status & (1 << CP0St_BEV)) {
- env->active_tc.PC = (int32_t)0xBFC00200;
+ env->active_tc.PC = env->exception_base + 0x200;
} else {
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
}
diff --git a/target-mips/translate.c b/target-mips/translate.c
index cc321e9..c302fa3 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -20169,6 +20169,7 @@ MIPSCPU *cpu_mips_init(const char *cpu_model)
cpu = MIPS_CPU(object_new(TYPE_MIPS_CPU));
env = &cpu->env;
env->cpu_model = def;
+ env->exception_base = (int32_t)0xBFC00000;
#ifndef CONFIG_USER_ONLY
mmu_init(env, def);
@@ -20191,6 +20192,12 @@ bool cpu_supports_cps_smp(const char *cpu_model)
return (def->CP0_Config3 & (1 << CP0C3_CMGCR)) != 0;
}
+void cpu_set_exception_base(int vp_index, target_ulong address)
+{
+ MIPSCPU *vp = MIPS_CPU(qemu_get_cpu(vp_index));
+ vp->env.exception_base = address;
+}
+
void cpu_state_reset(CPUMIPSState *env)
{
MIPSCPU *cpu = mips_env_get_cpu(env);
@@ -20281,7 +20288,7 @@ void cpu_state_reset(CPUMIPSState *env)
} else {
env->CP0_ErrorEPC = env->active_tc.PC;
}
- env->active_tc.PC = (int32_t)0xBFC00000;
+ env->active_tc.PC = env->exception_base;
env->CP0_Random = env->tlb->nb_tlb - 1;
env->tlb->tlb_in_use = env->tlb->nb_tlb;
env->CP0_Wired = 0;
--
2.7.4
- [Qemu-devel] [PULL 00/11] target-mips queue, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 01/11] hw/mips: implement GIC Interval Timer, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 03/11] hw/mips/cps: create GIC block inside CPS, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 05/11] hw/mips_cpc: make VP correctly start from the reset vector, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 02/11] hw/mips: implement Global Interrupt Controller, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 07/11] target-mips: replace MIPS64R6-generic with the real I6400 CPU model, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 04/11] target-mips: add exception base to MIPS CPU,
Leon Alrae <=
- [Qemu-devel] [PULL 06/11] hw/mips_cmgcr: implement RESET_BASE register in CM GCR, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 11/11] target-mips: enable 10-bit ASIDs in I6400 CPU, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 09/11] target-mips: change ASID type to hold more than 8 bits, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 08/11] target-mips: add ASID mask field and replace magic values, Leon Alrae, 2016/07/12
- [Qemu-devel] [PULL 10/11] target-mips: support CP0.Config4.AE bit, Leon Alrae, 2016/07/12
- Re: [Qemu-devel] [PULL 00/11] target-mips queue, Peter Maydell, 2016/07/12