Re: [Qemu-devel] [SeaBIOS] [PATCH v3] fw/msr_feature_control: add support to set MSR_IA32_FEATURE_CONTROL

[Haozhong Zhang]

On 07/06/16 11:00, Laszlo Ersek wrote:
> On 07/06/16 10:48, Haozhong Zhang wrote:
> > On 07/06/16 09:44, Laszlo Ersek wrote:
> >> On 07/06/16 08:49, Haozhong Zhang wrote:
> >>> On 07/06/16 08:42, Laszlo Ersek wrote:
> >>>> On 07/06/16 08:28, Haozhong Zhang wrote:
> >>>>> Hi Ashok,
> >>>>>
> >>>>> On 07/06/16 02:18, Paolo Bonzini wrote:
> >>>>>>> I forgot to restore MSR_IA32_FEATURE_CONTROL in the resume path, and
> >>>>>>> MSR_IA32_FEATURE_CONTROL is zero after S3 resume.
> >>>>>>
> >>>>>> This is a bug.  Sorry Laszlo. :)
> >>>>>>
> >>>>>>> Not restore MSR_IA32_FEATURE_CONTROL during S3 resume does not affect
> >>>>>>> at least Linux guest (tested 4.5). Current QEMU may advise the guest
> >>>>>>> firmware to set bit 20 (for LMCE), bit 2 (for VMX) and bit 0 (lock
> >>>>>>> bit).
> >>>>>>> - For LMCE, Linux only checks bit 20 and bit 0 at boot time and then
> >>>>>>>   keeps using the result even after resume.
> >>>>>>
> >>>>>> On real hardware, LMCE would not be enabled after resume.  I'm not
> >>>>>> sure what would happen, but it wouldn't be good.
> >>>>>
> >>>>> Could you help to check if the LMCE bit in MSR_IA32_FEATURE_CONTROL is
> >>>>> set after S3 resume on the real hardware?
> >>>>
> >>>> The SDM says that IA32_FEATURE_CONTROL is zeroed on logical processor 
> >>>> reset.
> >>>>
> >>>>   23.7 ENABLING AND ENTERING VMX OPERATION
> >>>>
> >>>>   [...] VMXON is also controlled by the IA32_FEATURE_CONTROL MSR (MSR
> >>>>   address 3AH). This MSR is cleared to zero when a logical processor is
> >>>>   reset. [...]
> >>>>
> >>>
> >>> Ah, I missed a bit in my question. I meant to check whether the
> >>> firmware on the real machine sets the LMCE bit and other necessary
> >>> bits in MSR_IA32_FEATURE_CONTROL after S3 resume.
> >>>
> >>
> >> I attached a minimal kernel module (reproducer / tester) to the github
> >> issue here:
> >>
> >> https://github.com/tianocore/edk2/issues/97#issuecomment-230697897
> >>
> >> We can use it for both testing the feature in guests, and for querying
> >> the MSR on physical machines.
> >>
> > 
> > Thanks for the kernel module! In fact, I'm using the rdmsr command
> > provided by msr-tools (which is included in some Linux distros).
> 
> Welp, that package is available on RHEL-7 too (from EPEL), I just didn't
> have it installed. (I guessed that the command would be called "rdmsr",
> and tried to run it, but when that failed, I didn't look for any packages.)
> 
> >> Specifically on my ThinkPad W541, the MSR has value 0x5:
> >>
> >> [ 2885.877339] MSR 0x3a on CPU 0: 0x5
> >> [ 2908.151693] MSR 0x3a on CPU 1: 0x5
> >>
> >> which, according to
> >>
> >> #define FEATURE_CONTROL_LOCKED                             (1<<0)
> >> #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX   (1<<1)
> >> #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX  (1<<2)
> >> #define FEATURE_CONTROL_LMCE                               (1<<20)
> >>
> >> corresponds to
> >>
> >> (FEATURE_CONTROL_LOCKED | FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX).
> >>
> >> FEATURE_CONTROL_LMCE is not set at all. (I didn't do any S3 cycles in my
> >> current laptopt boot.)
> >>
> >> My CPU is i7-4810MQ. It's a pretty modern laptop, so I think it is
> >> capable of LMCE, hardware-wise (if LMCE is hw-dependent, to begin with).
> >>
> > 
> > LMCE is supported only by server CPUs (Skylake-EX or later) and not
> > available on desktop CPUs.
> > 
> > For test in guest, you could follow what I added in "How to verify?"
> > https://github.com/tianocore/edk2/issues/97.
> 
> Great, apparently I can't even read. Those steps are in the first
> comment. :/
>

I supposed every modification in github issues would trigger mail
notifications to others, but apparently it does not. I'll take care in
the future.

Haozhong