Re: [Qemu-devel] [PATCH v3 18/35] target-*: Don't redefine cpu_exec()

[Paolo Bonzini]

On 18/07/2015 11:40, Peter Crosthwaite wrote:
> This function needs to be converted to QOM hook and virtualised for
> multi-arch. This rename interferes, as cpu-qom will not have access
> to the renaming causing name divergence. This rename doesn't really do
> anything anyway so just delete it.
> 
> Signed-off-by: Peter Crosthwaite <address@hidden>
> ---
>  include/exec/cpu-all.h  |  2 ++
>  linux-user/main.c       | 28 ++++++++++++++--------------
>  target-alpha/cpu.h      |  2 --
>  target-arm/cpu.h        |  2 --
>  target-cris/cpu.h       |  2 --
>  target-i386/cpu.h       |  2 --
>  target-lm32/cpu.h       |  2 --
>  target-m68k/cpu.h       |  2 --
>  target-microblaze/cpu.h |  2 --
>  target-mips/cpu.h       |  2 --
>  target-moxie/cpu.h      |  2 --
>  target-openrisc/cpu.h   |  2 --
>  target-ppc/cpu.h        |  2 --
>  target-s390x/cpu.h      |  2 --
>  target-sh4/cpu.h        |  2 --
>  target-sparc/cpu.h      |  2 --
>  target-tricore/cpu.h    |  2 --
>  target-unicore32/cpu.h  |  1 -
>  target-xtensa/cpu.h     |  2 --
>  19 files changed, 16 insertions(+), 47 deletions(-)
> 
> diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h
> index ea6a9a6..e2fc9ca 100644
> --- a/include/exec/cpu-all.h
> +++ b/include/exec/cpu-all.h
> @@ -331,4 +331,6 @@ void qemu_mutex_unlock_ramlist(void);
>  int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,
>                          uint8_t *buf, int len, int is_write);
>  
> +int cpu_exec(CPUState *cpu);
> +
>  #endif /* CPU_ALL_H */
> diff --git a/linux-user/main.c b/linux-user/main.c
> index fdee981..d2bfea4 100644
> --- a/linux-user/main.c
> +++ b/linux-user/main.c
> @@ -280,7 +280,7 @@ void cpu_loop(CPUX86State *env)
>  
>      for(;;) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_x86_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch(trapnr) {
>          case 0x80:
> @@ -674,7 +674,7 @@ void cpu_loop(CPUARMState *env)
>  
>      for(;;) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_arm_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch(trapnr) {
>          case EXCP_UDEF:
> @@ -1005,7 +1005,7 @@ void cpu_loop(CPUARMState *env)
>  
>      for (;;) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_arm_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>  
>          switch (trapnr) {
> @@ -1084,7 +1084,7 @@ void cpu_loop(CPUUniCore32State *env)
>  
>      for (;;) {
>          cpu_exec_start(cs);
> -        trapnr = uc32_cpu_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch (trapnr) {
>          case UC32_EXCP_PRIV:
> @@ -1285,7 +1285,7 @@ void cpu_loop (CPUSPARCState *env)
>  
>      while (1) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_sparc_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>  
>          /* Compute PSR before exposing state.  */
> @@ -1565,7 +1565,7 @@ void cpu_loop(CPUPPCState *env)
>  
>      for(;;) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_ppc_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch(trapnr) {
>          case POWERPC_EXCP_NONE:
> @@ -2417,7 +2417,7 @@ void cpu_loop(CPUMIPSState *env)
>  
>      for(;;) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_mips_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch(trapnr) {
>          case EXCP_SYSCALL:
> @@ -2654,7 +2654,7 @@ void cpu_loop(CPUOpenRISCState *env)
>  
>      for (;;) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_openrisc_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          gdbsig = 0;
>  
> @@ -2744,7 +2744,7 @@ void cpu_loop(CPUSH4State *env)
>  
>      while (1) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_sh4_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>  
>          switch (trapnr) {
> @@ -2806,7 +2806,7 @@ void cpu_loop(CPUCRISState *env)
>      
>      while (1) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_cris_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch (trapnr) {
>          case 0xaa:
> @@ -2867,7 +2867,7 @@ void cpu_loop(CPUMBState *env)
>      
>      while (1) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_mb_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch (trapnr) {
>          case 0xaa:
> @@ -2972,7 +2972,7 @@ void cpu_loop(CPUM68KState *env)
>  
>      for(;;) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_m68k_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch(trapnr) {
>          case EXCP_ILLEGAL:
> @@ -3111,7 +3111,7 @@ void cpu_loop(CPUAlphaState *env)
>  
>      while (1) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_alpha_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>  
>          /* All of the traps imply a transition through PALcode, which
> @@ -3299,7 +3299,7 @@ void cpu_loop(CPUS390XState *env)
>  
>      while (1) {
>          cpu_exec_start(cs);
> -        trapnr = cpu_s390x_exec(cs);
> +        trapnr = cpu_exec(cs);
>          cpu_exec_end(cs);
>          switch (trapnr) {
>          case EXCP_INTERRUPT:
> diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h
> index 91c56d6..fbdabb2 100644
> --- a/target-alpha/cpu.h
> +++ b/target-alpha/cpu.h
> @@ -288,7 +288,6 @@ struct CPUAlphaState {
>  };
>  
>  #define cpu_list alpha_cpu_list
> -#define cpu_exec cpu_alpha_exec
>  #define cpu_gen_code cpu_alpha_gen_code
>  #define cpu_signal_handler cpu_alpha_signal_handler
>  
> @@ -431,7 +430,6 @@ AlphaCPU *cpu_alpha_init(const char *cpu_model);
>  #define cpu_init(cpu_model) CPU(cpu_alpha_init(cpu_model))
>  
>  void alpha_cpu_list(FILE *f, fprintf_function cpu_fprintf);
> -int cpu_alpha_exec(CPUState *cpu);
>  /* you can call this signal handler from your SIGBUS and SIGSEGV
>     signal handlers to inform the virtual CPU of exceptions. non zero
>     is returned if the signal was handled by the virtual CPU.  */
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 7e89152..7282833 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -499,7 +499,6 @@ typedef struct CPUARMState {
>  #include "cpu-qom.h"
>  
>  ARMCPU *cpu_arm_init(const char *cpu_model);
> -int cpu_arm_exec(CPUState *cpu);
>  uint32_t do_arm_semihosting(CPUARMState *env);
>  void aarch64_sync_32_to_64(CPUARMState *env);
>  void aarch64_sync_64_to_32(CPUARMState *env);
> @@ -1586,7 +1585,6 @@ static inline bool arm_excp_unmasked(CPUState *cs, 
> unsigned int excp_idx,
>  
>  #define cpu_init(cpu_model) CPU(cpu_arm_init(cpu_model))
>  
> -#define cpu_exec cpu_arm_exec
>  #define cpu_gen_code cpu_arm_gen_code
>  #define cpu_signal_handler cpu_arm_signal_handler
>  #define cpu_list arm_cpu_list
> diff --git a/target-cris/cpu.h b/target-cris/cpu.h
> index d422e35..cf8ea10 100644
> --- a/target-cris/cpu.h
> +++ b/target-cris/cpu.h
> @@ -176,7 +176,6 @@ typedef struct CPUCRISState {
>  #include "cpu-qom.h"
>  
>  CRISCPU *cpu_cris_init(const char *cpu_model);
> -int cpu_cris_exec(CPUState *cpu);
>  /* you can call this signal handler from your SIGBUS and SIGSEGV
>     signal handlers to inform the virtual CPU of exceptions. non zero
>     is returned if the signal was handled by the virtual CPU.  */
> @@ -223,7 +222,6 @@ enum {
>  
>  #define cpu_init(cpu_model) CPU(cpu_cris_init(cpu_model))
>  
> -#define cpu_exec cpu_cris_exec
>  #define cpu_gen_code cpu_cris_gen_code
>  #define cpu_signal_handler cpu_cris_signal_handler
>  
> diff --git a/target-i386/cpu.h b/target-i386/cpu.h
> index ead2832..ff01152 100644
> --- a/target-i386/cpu.h
> +++ b/target-i386/cpu.h
> @@ -987,7 +987,6 @@ typedef struct CPUX86State {
>  
>  X86CPU *cpu_x86_init(const char *cpu_model);
>  X86CPU *cpu_x86_create(const char *cpu_model, Error **errp);
> -int cpu_x86_exec(CPUState *cpu);
>  void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>  void x86_cpudef_setup(void);
>  int cpu_x86_support_mca_broadcast(CPUX86State *env);
> @@ -1186,7 +1185,6 @@ uint64_t cpu_get_tsc(CPUX86State *env);
>  
>  #define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
>  
> -#define cpu_exec cpu_x86_exec
>  #define cpu_gen_code cpu_x86_gen_code
>  #define cpu_signal_handler cpu_x86_signal_handler
>  #define cpu_list x86_cpu_list
> diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h
> index 944777d..80a42e9 100644
> --- a/target-lm32/cpu.h
> +++ b/target-lm32/cpu.h
> @@ -199,7 +199,6 @@ static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
>  #include "cpu-qom.h"
>  
>  LM32CPU *cpu_lm32_init(const char *cpu_model);
> -int cpu_lm32_exec(CPUState *cpu);
>  /* you can call this signal handler from your SIGBUS and SIGSEGV
>     signal handlers to inform the virtual CPU of exceptions. non zero
>     is returned if the signal was handled by the virtual CPU.  */
> @@ -220,7 +219,6 @@ bool lm32_cpu_do_semihosting(CPUState *cs);
>  #define cpu_init(cpu_model) CPU(cpu_lm32_init(cpu_model))
>  
>  #define cpu_list lm32_cpu_list
> -#define cpu_exec cpu_lm32_exec
>  #define cpu_gen_code cpu_lm32_gen_code
>  #define cpu_signal_handler cpu_lm32_signal_handler
>  
> diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h
> index 9a62f6c..5865235 100644
> --- a/target-m68k/cpu.h
> +++ b/target-m68k/cpu.h
> @@ -117,7 +117,6 @@ typedef struct CPUM68KState {
>  void m68k_tcg_init(void);
>  void m68k_cpu_init_gdb(M68kCPU *cpu);
>  M68kCPU *cpu_m68k_init(const char *cpu_model);
> -int cpu_m68k_exec(CPUState *cpu);
>  /* you can call this signal handler from your SIGBUS and SIGSEGV
>     signal handlers to inform the virtual CPU of exceptions. non zero
>     is returned if the signal was handled by the virtual CPU.  */
> @@ -214,7 +213,6 @@ void register_m68k_insns (CPUM68KState *env);
>  
>  #define cpu_init(cpu_model) CPU(cpu_m68k_init(cpu_model))
>  
> -#define cpu_exec cpu_m68k_exec
>  #define cpu_gen_code cpu_m68k_gen_code
>  #define cpu_signal_handler cpu_m68k_signal_handler
>  #define cpu_list m68k_cpu_list
> diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
> index 7e20e59..86dd1ce 100644
> --- a/target-microblaze/cpu.h
> +++ b/target-microblaze/cpu.h
> @@ -281,7 +281,6 @@ struct CPUMBState {
>  
>  void mb_tcg_init(void);
>  MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
> -int cpu_mb_exec(CPUState *cpu);
>  /* you can call this signal handler from your SIGBUS and SIGSEGV
>     signal handlers to inform the virtual CPU of exceptions. non zero
>     is returned if the signal was handled by the virtual CPU.  */
> @@ -296,7 +295,6 @@ int cpu_mb_signal_handler(int host_signum, void *pinfo,
>  
>  #define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))
>  
> -#define cpu_exec cpu_mb_exec
>  #define cpu_gen_code cpu_mb_gen_code
>  #define cpu_signal_handler cpu_mb_signal_handler
>  
> diff --git a/target-mips/cpu.h b/target-mips/cpu.h
> index 075c561..54273c6 100644
> --- a/target-mips/cpu.h
> +++ b/target-mips/cpu.h
> @@ -620,7 +620,6 @@ void mips_cpu_unassigned_access(CPUState *cpu, hwaddr 
> addr,
>  
>  void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf);
>  
> -#define cpu_exec cpu_mips_exec
>  #define cpu_gen_code cpu_mips_gen_code
>  #define cpu_signal_handler cpu_mips_signal_handler
>  #define cpu_list mips_cpu_list
> @@ -746,7 +745,6 @@ enum {
>   */
>  #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0
>  
> -int cpu_mips_exec(CPUState *cpu);
>  void mips_tcg_init(void);
>  MIPSCPU *cpu_mips_init(const char *cpu_model);
>  int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc);
> diff --git a/target-moxie/cpu.h b/target-moxie/cpu.h
> index 29572aa..5be9d02 100644
> --- a/target-moxie/cpu.h
> +++ b/target-moxie/cpu.h
> @@ -112,7 +112,6 @@ static inline MoxieCPU *moxie_env_get_cpu(CPUMoxieState 
> *env)
>  #define ENV_OFFSET offsetof(MoxieCPU, env)
>  
>  MoxieCPU *cpu_moxie_init(const char *cpu_model);
> -int cpu_moxie_exec(CPUState *cpu);
>  void moxie_cpu_do_interrupt(CPUState *cs);
>  void moxie_cpu_dump_state(CPUState *cpu, FILE *f,
>                            fprintf_function cpu_fprintf, int flags);
> @@ -123,7 +122,6 @@ int cpu_moxie_signal_handler(int host_signum, void *pinfo,
>  
>  #define cpu_init(cpu_model) CPU(cpu_moxie_init(cpu_model))
>  
> -#define cpu_exec cpu_moxie_exec
>  #define cpu_gen_code cpu_moxie_gen_code
>  #define cpu_signal_handler cpu_moxie_signal_handler
>  
> diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
> index 36c4f20..9e8db1f 100644
> --- a/target-openrisc/cpu.h
> +++ b/target-openrisc/cpu.h
> @@ -346,7 +346,6 @@ static inline OpenRISCCPU 
> *openrisc_env_get_cpu(CPUOpenRISCState *env)
>  OpenRISCCPU *cpu_openrisc_init(const char *cpu_model);
>  
>  void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf);
> -int cpu_openrisc_exec(CPUState *cpu);
>  void openrisc_cpu_do_interrupt(CPUState *cpu);
>  bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req);
>  void openrisc_cpu_dump_state(CPUState *cpu, FILE *f,
> @@ -360,7 +359,6 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr 
> address,
>  int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
>  
>  #define cpu_list cpu_openrisc_list
> -#define cpu_exec cpu_openrisc_exec
>  #define cpu_gen_code cpu_openrisc_gen_code
>  #define cpu_signal_handler cpu_openrisc_signal_handler
>  
> diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
> index 6f76674..9b79f13 100644
> --- a/target-ppc/cpu.h
> +++ b/target-ppc/cpu.h
> @@ -1164,7 +1164,6 @@ do {                                            \
>  PowerPCCPU *cpu_ppc_init(const char *cpu_model);
>  void ppc_translate_init(void);
>  void gen_update_current_nip(void *opaque);
> -int cpu_ppc_exec (CPUState *s);
>  /* you can call this signal handler from your SIGBUS and SIGSEGV
>     signal handlers to inform the virtual CPU of exceptions. non zero
>     is returned if the signal was handled by the virtual CPU.  */
> @@ -1240,7 +1239,6 @@ int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, 
> uint32_t val);
>  
>  #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
>  
> -#define cpu_exec cpu_ppc_exec
>  #define cpu_gen_code cpu_ppc_gen_code
>  #define cpu_signal_handler cpu_ppc_signal_handler
>  #define cpu_list ppc_cpu_list
> diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h
> index 63aebf4..4ee4d7f 100644
> --- a/target-s390x/cpu.h
> +++ b/target-s390x/cpu.h
> @@ -417,7 +417,6 @@ void trigger_pgm_exception(CPUS390XState *env, uint32_t 
> code, uint32_t ilen);
>  
>  S390CPU *cpu_s390x_init(const char *cpu_model);
>  void s390x_translate_init(void);
> -int cpu_s390x_exec(CPUState *cpu);
>  
>  /* you can call this signal handler from your SIGBUS and SIGSEGV
>     signal handlers to inform the virtual CPU of exceptions. non zero
> @@ -599,7 +598,6 @@ bool css_present(uint8_t cssid);
>  #endif
>  
>  #define cpu_init(model) CPU(cpu_s390x_init(model))
> -#define cpu_exec cpu_s390x_exec
>  #define cpu_gen_code cpu_s390x_gen_code
>  #define cpu_signal_handler cpu_s390x_signal_handler
>  
> diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h
> index 34bb3d7..3cd1b19 100644
> --- a/target-sh4/cpu.h
> +++ b/target-sh4/cpu.h
> @@ -193,7 +193,6 @@ typedef struct CPUSH4State {
>  
>  void sh4_translate_init(void);
>  SuperHCPU *cpu_sh4_init(const char *cpu_model);
> -int cpu_sh4_exec(CPUState *s);
>  int cpu_sh4_signal_handler(int host_signum, void *pinfo,
>                             void *puc);
>  int superh_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
> @@ -226,7 +225,6 @@ void cpu_load_tlb(CPUSH4State * env);
>  
>  #define cpu_init(cpu_model) CPU(cpu_sh4_init(cpu_model))
>  
> -#define cpu_exec cpu_sh4_exec
>  #define cpu_gen_code cpu_sh4_gen_code
>  #define cpu_signal_handler cpu_sh4_signal_handler
>  #define cpu_list sh4_cpu_list
> diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
> index 0522b65..cc26587 100644
> --- a/target-sparc/cpu.h
> +++ b/target-sparc/cpu.h
> @@ -537,7 +537,6 @@ int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
>  void gen_intermediate_code_init(CPUSPARCState *env);
>  
>  /* cpu-exec.c */
> -int cpu_sparc_exec(CPUState *cpu);
>  
>  /* win_helper.c */
>  target_ulong cpu_get_psr(CPUSPARCState *env1);
> @@ -597,7 +596,6 @@ int cpu_sparc_signal_handler(int host_signum, void 
> *pinfo, void *puc);
>  #define cpu_init(cpu_model) CPU(cpu_sparc_init(cpu_model))
>  #endif
>  
> -#define cpu_exec cpu_sparc_exec
>  #define cpu_gen_code cpu_sparc_gen_code
>  #define cpu_signal_handler cpu_sparc_signal_handler
>  #define cpu_list sparc_cpu_list
> diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h
> index 916ee27..fa49d9d 100644
> --- a/target-tricore/cpu.h
> +++ b/target-tricore/cpu.h
> @@ -346,7 +346,6 @@ void psw_write(CPUTriCoreState *env, uint32_t val);
>  
>  void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf);
>  
> -#define cpu_exec cpu_tricore_exec
>  #define cpu_signal_handler cpu_tricore_signal_handler
>  #define cpu_list tricore_cpu_list
>  
> @@ -372,7 +371,6 @@ enum {
>  };
>  
>  void cpu_state_reset(CPUTriCoreState *s);
> -int cpu_tricore_exec(CPUState *cpu);
>  void tricore_tcg_init(void);
>  int cpu_tricore_signal_handler(int host_signum, void *pinfo, void *puc);
>  
> diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h
> index 45e31e5..ba885d3 100644
> --- a/target-unicore32/cpu.h
> +++ b/target-unicore32/cpu.h
> @@ -122,7 +122,6 @@ void cpu_asr_write(CPUUniCore32State *env1, target_ulong 
> val, target_ulong mask)
>  #define UC32_HWCAP_CMOV                 4 /* 1 << 2 */
>  #define UC32_HWCAP_UCF64                8 /* 1 << 3 */
>  
> -#define cpu_exec                        uc32_cpu_exec
>  #define cpu_signal_handler              uc32_cpu_signal_handler
>  
>  int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
> diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
> index 96bfc82..e7c2588 100644
> --- a/target-xtensa/cpu.h
> +++ b/target-xtensa/cpu.h
> @@ -382,7 +382,6 @@ typedef struct CPUXtensaState {
>  
>  #include "cpu-qom.h"
>  
> -#define cpu_exec cpu_xtensa_exec
>  #define cpu_gen_code cpu_xtensa_gen_code
>  #define cpu_signal_handler cpu_xtensa_signal_handler
>  #define cpu_list xtensa_cpu_list
> @@ -399,7 +398,6 @@ XtensaCPU *cpu_xtensa_init(const char *cpu_model);
>  
>  void xtensa_translate_init(void);
>  void xtensa_breakpoint_handler(CPUState *cs);
> -int cpu_xtensa_exec(CPUState *cpu);
>  void xtensa_finalize_config(XtensaConfig *config);
>  void xtensa_register_core(XtensaConfigList *node);
>  void check_interrupts(CPUXtensaState *s);
> 

I'm queuing this patch, because why not. :)

Paolo