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[Qemu-devel] [PATCH 13/25] target-openrisc: Enable trap, csync, msync, p
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 13/25] target-openrisc: Enable trap, csync, msync, psync for user mode |
Date: |
Mon, 13 Jun 2016 16:58:13 -0700 |
Not documented as disabled for user mode.
Reviewed-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-openrisc/translate.c | 32 --------------------------------
1 file changed, 32 deletions(-)
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 4dde531..d028612 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1043,52 +1043,20 @@ static void dec_sys(DisasContext *dc, uint32_t insn)
case 0x100: /* l.trap */
LOG_DIS("l.trap %d\n", K16);
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
tcg_gen_movi_tl(cpu_pc, dc->pc);
gen_exception(dc, EXCP_TRAP);
-#endif
break;
case 0x300: /* l.csync */
LOG_DIS("l.csync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
break;
case 0x200: /* l.msync */
LOG_DIS("l.msync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
break;
case 0x270: /* l.psync */
LOG_DIS("l.psync\n");
-#if defined(CONFIG_USER_ONLY)
- return;
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
- gen_illegal_exception(dc);
- return;
- }
-#endif
break;
default:
--
2.5.5
- [Qemu-devel] [PATCH 00/25] target-openrisc improvements, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 01/25] target-openrisc: Always enable OPENRISC_DISAS, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 06/25] target-openrisc: Put SR[OVE] in TB flags, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 05/25] target-openrisc: Use movcond where appropriate, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 08/25] target-openrisc: Set flags on helpers, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 03/25] target-openrisc: Invert the decoding in dec_calc, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 04/25] target-openrisc: Keep SR_F in a separate variable, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 07/25] target-openrisc: Keep SR_CY and SR_OV in a separate variables, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 02/25] target-openrisc: Streamline arithmetic and OVE, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 12/25] target-openrisc: Enable m[tf]spr from user mode, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 13/25] target-openrisc: Enable trap, csync, msync, psync for user mode,
Richard Henderson <=
- [Qemu-devel] [PATCH 11/25] target-openrisc: Rationalize immediate extraction, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 14/25] target-openrisc: Implement muld, muldu, macu, msbu, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 19/25] target-openrisc: Tidy ppc/npc implementation, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 09/25] target-openrisc: Implement ff1 and fl1 for 64-bit, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 21/25] target-openrisc: Tidy insn dumping, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 16/25] target-openrisc: Write back result before FPE exception, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 18/25] target-openrisc: Implement l.adrp, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 20/25] target-openrisc: Optimize l.jal to next, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 10/25] target-openrisc: Represent MACHI:MACLO as a single unit, Richard Henderson, 2016/06/13
- [Qemu-devel] [PATCH 17/25] target-openrisc: Implement lwa, swa, Richard Henderson, 2016/06/13