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[Qemu-devel] [PATCH 6/9] target-avr: adding helpers for IN, OUT, SLEEP,
From: |
Michael Rolnik |
Subject: |
[Qemu-devel] [PATCH 6/9] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions |
Date: |
Fri, 3 Jun 2016 03:40:17 +0300 |
Signed-off-by: Michael Rolnik <address@hidden>
---
target-avr/helper.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++-----
target-avr/helper.h | 5 +++
2 files changed, 111 insertions(+), 11 deletions(-)
diff --git a/target-avr/helper.c b/target-avr/helper.c
index bb47a87..b93589a 100644
--- a/target-avr/helper.c
+++ b/target-avr/helper.c
@@ -31,7 +31,7 @@
bool avr_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
- CPUClass *cc = CPU_GET_CLASS(cs);
+ CPUClass *cc = CPU_GET_CLASS(cs);
AVRCPU *cpu = AVR_CPU(cs);
CPUAVRState *env = &cpu->env;
@@ -49,7 +49,7 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
}
if (interrupt_request & CPU_INTERRUPT_HARD) {
if (cpu_interrupts_enabled(env) && env->intsrc != 0) {
- int index = __builtin_ffs(env->intsrc) - 1;
+ int index = __builtin_ffs(env->intsrc) - 1;
cs->exception_index = EXCP_INT(index);
cc->do_interrupt(cs);
@@ -64,18 +64,18 @@ bool avr_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
void avr_cpu_do_interrupt(CPUState *cs)
{
- AVRCPU *cpu = AVR_CPU(cs);
- CPUAVRState *env = &cpu->env;
+ AVRCPU *cpu = AVR_CPU(cs);
+ CPUAVRState *env = &cpu->env;
- uint32_t ret = env->pc;
- int vector;
- int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
- int base = 0; /* TODO: where to get it */
+ uint32_t ret = env->pc;
+ int vector;
+ int size = avr_feature(env, AVR_FEATURE_JMP_CALL) ? 2 : 1;
+ int base = 0; /* TODO: where to get it */
if (cs->exception_index == EXCP_RESET) {
- vector = 0;
+ vector = 0;
} else if (env->intsrc != 0) {
- vector = __builtin_ffs(env->intsrc);
+ vector = __builtin_ffs(env->intsrc);
}
if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) {
@@ -95,7 +95,7 @@ void avr_cpu_do_interrupt(CPUState *cs)
env->pc = base + vector * size;
}
- env->sregI = 0; /* clear Global Interrupt Flag */
+ env->sregI = 0; /* clear Global Interrupt Flag */
cs->exception_index = -1;
}
@@ -136,6 +136,21 @@ void tlb_fill(CPUState *cs, target_ulong vaddr, int
is_write, int mmu_idx, uintp
tlb_set_page_with_attrs(cs, vaddr, paddr, attrs, prot, mmu_idx, page_size);
}
+void helper_sleep(CPUAVRState *env)
+{
+ CPUState *cs = CPU(avr_env_get_cpu(env));
+
+ cs->exception_index = EXCP_HLT;
+ cpu_loop_exit(cs);
+}
+void helper_unsupported(CPUAVRState *env)
+{
+ CPUState *cs = CPU(avr_env_get_cpu(env));
+
+ cs->exception_index = EXCP_DEBUG;
+ cpu_dump_state(cs, stderr, fprintf, 0);
+ cpu_loop_exit(cs);
+}
void helper_debug(CPUAVRState *env)
{
@@ -145,3 +160,83 @@ void helper_debug(CPUAVRState *env)
cpu_loop_exit(cs);
}
+void helper_wdr(CPUAVRState *env)
+{
+ CPUState *cs = CPU(avr_env_get_cpu(env));
+
+ cs->exception_index = EXCP_DEBUG;
+ cpu_loop_exit(cs);
+}
+
+target_ulong helper_inb(CPUAVRState *env, uint32_t port)
+{
+ printf("in: io[%02x]\n", port);
+
+ switch (port) {
+ case 0x3b: {
+ return env->rampZ; /* RAMPZ */
+ }
+ case 0x3d: { /* SPL */
+ return env->sp & 0x00ff;
+ }
+ case 0x3e: { /* SPH */
+ return env->sp >> 8;
+ }
+ case 0x3f: { /* SREG */
+ uint8_t sreg;
+ sreg = (env->sregC & 0x01) << 0
+ | (env->sregZ & 0x01) << 1
+ | (env->sregN & 0x01) << 2
+ | (env->sregV & 0x01) << 3
+ | (env->sregS & 0x01) << 4
+ | (env->sregH & 0x01) << 5
+ | (env->sregT & 0x01) << 6
+ | (env->sregI & 0x01) << 7;
+ return sreg;
+ }
+ }
+ return 0;
+}
+
+void helper_outb(CPUAVRState *env, uint32_t port, uint32_t data)
+{
+ printf("out:%02x -> io[%02x]\n", data, port);
+
+ data &= 0x000000ff;
+
+ switch (port) {
+ case 0x04: {
+ qemu_irq irq;
+ CPUState *cpu = CPU(avr_env_get_cpu(env));
+ irq = qdev_get_gpio_in(DEVICE(cpu), 3);
+ qemu_set_irq(irq, 1);
+ break;
+ }
+ case 0x3b: {
+ env->rampZ = data & 0x01; /* RAMPZ */
+ break;
+ }
+ case 0x3d: { /* SPL */
+ if (avr_feature(env, AVR_FEATURE_2_BYTE_SP)) {
+ env->sp = (env->sp & 0xff00) | (data);
+ }
+ break;
+ }
+ case 0x3e: { /* SPH */
+ env->sp = (env->sp & 0x00ff) | (data << 8);
+ break;
+ }
+ case 0x3f: { /* SREG */
+ env->sregC = (data >> 0) & 0x01;
+ env->sregZ = (data >> 1) & 0x01;
+ env->sregN = (data >> 2) & 0x01;
+ env->sregV = (data >> 3) & 0x01;
+ env->sregS = (data >> 4) & 0x01;
+ env->sregH = (data >> 5) & 0x01;
+ env->sregT = (data >> 6) & 0x01;
+ env->sregI = (data >> 7) & 0x01;
+ break;
+ }
+ }
+}
+
diff --git a/target-avr/helper.h b/target-avr/helper.h
index b5ef3bf..82f440a 100644
--- a/target-avr/helper.h
+++ b/target-avr/helper.h
@@ -18,4 +18,9 @@
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
+DEF_HELPER_1(wdr, void, env)
DEF_HELPER_1(debug, void, env)
+DEF_HELPER_1(sleep, void, env)
+DEF_HELPER_1(unsupported, void, env)
+DEF_HELPER_3(outb, void, env, i32, i32)
+DEF_HELPER_2(inb, tl, env, i32)
--
2.4.9 (Apple Git-60)
- [Qemu-devel] AVR cores, Michael Rolnik, 2016/06/02
- [Qemu-devel] [PATCH 3/9] target-avr: adding a sample AVR board, Michael Rolnik, 2016/06/02
- [Qemu-devel] [PATCH 1/9] target-avr: AVR cores support is added. 1. basic CPU structure 2. registers 3. no instructions, Michael Rolnik, 2016/06/02
- [Qemu-devel] [PATCH 2/9] target-avr: adding AVR CPU features/flavors, Michael Rolnik, 2016/06/02
- [Qemu-devel] [PATCH 7/9] target-avr: adding instruction decoder, Michael Rolnik, 2016/06/02
- [Qemu-devel] [PATCH 6/9] target-avr: adding helpers for IN, OUT, SLEEP, WBR & unsupported instructions,
Michael Rolnik <=
- [Qemu-devel] [PATCH 5/9] target-avr: adding AVR interrupt handling, Michael Rolnik, 2016/06/02
- [Qemu-devel] [PATCH 4/9] target-avr: adding instructions encodings, Michael Rolnik, 2016/06/02
- [Qemu-devel] [PATCH 9/9] target-avr: updating translate.c to use instructions translation, Michael Rolnik, 2016/06/02
- [Qemu-devel] [PATCH 8/9] target-avr: adding instruction translation, Michael Rolnik, 2016/06/02