[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] ARM IRQ Generation

From: Karthik
Subject: [Qemu-devel] ARM IRQ Generation
Date: Wed, 25 May 2016 16:17:25 +0530


I am working on emulating an Spansion micro with ARM Cortex R5F Core.

It has got an Interrupt Controller which accepts multiple interrupts and
generates the IRQ to the CPU based on register settings.

Now an timer module calls the qemu_irq_pulse() to signal the Interrupt
Controller (IC). The interrupt handler in the IC is called with the correct
irq number with level 1 and immediately followed by level 0. The IC in turn
signals the CPU using qemu_set_irq with level 1 and 0.

In this case the ARM CPU is not interrupted at all and there is no
exception generated, because the irq is lowered before the CPU is

There is a delay between qemu_set_irq() and the ARM CPU getting interrupted.
I don't see any delay between timer and interrupt controller.

Any help will be much appreciated. Thank you.

Best regards,

reply via email to

[Prev in Thread] Current Thread [Next in Thread]