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[Qemu-devel] [PULL 06/24] ioapic: keep RO bits for IOAPIC entry
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 06/24] ioapic: keep RO bits for IOAPIC entry |
Date: |
Mon, 23 May 2016 17:09:41 +0200 |
From: Peter Xu <address@hidden>
Currently IOAPIC RO bits can be written. To be better aligned with
hardware, we should let them read-only.
Reviewed-by: Radim Krčmář <address@hidden>
Signed-off-by: Peter Xu <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Paolo Bonzini <address@hidden>
---
hw/intc/ioapic.c | 4 ++++
include/hw/i386/ioapic_internal.h | 5 +++++
2 files changed, 9 insertions(+)
diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c
index 4f42b91..c27ee83 100644
--- a/hw/intc/ioapic.c
+++ b/hw/intc/ioapic.c
@@ -281,6 +281,7 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
default:
index = (s->ioregsel - IOAPIC_REG_REDTBL_BASE) >> 1;
if (index >= 0 && index < IOAPIC_NUM_PINS) {
+ uint64_t ro_bits = s->ioredtbl[index] & IOAPIC_RO_BITS;
if (s->ioregsel & 1) {
s->ioredtbl[index] &= 0xffffffff;
s->ioredtbl[index] |= (uint64_t)val << 32;
@@ -288,6 +289,9 @@ ioapic_mem_write(void *opaque, hwaddr addr, uint64_t val,
s->ioredtbl[index] &= ~0xffffffffULL;
s->ioredtbl[index] |= val;
}
+ /* restore RO bits */
+ s->ioredtbl[index] &= IOAPIC_RW_BITS;
+ s->ioredtbl[index] |= ro_bits;
ioapic_service(s);
}
}
diff --git a/include/hw/i386/ioapic_internal.h
b/include/hw/i386/ioapic_internal.h
index 797ed47..cab9e67 100644
--- a/include/hw/i386/ioapic_internal.h
+++ b/include/hw/i386/ioapic_internal.h
@@ -47,6 +47,11 @@
#define IOAPIC_LVT_DEST_MODE (1 << IOAPIC_LVT_DEST_MODE_SHIFT)
#define IOAPIC_LVT_DELIV_MODE (7 << IOAPIC_LVT_DELIV_MODE_SHIFT)
+/* Bits that are read-only for IOAPIC entry */
+#define IOAPIC_RO_BITS (IOAPIC_LVT_REMOTE_IRR | \
+ IOAPIC_LVT_DELIV_STATUS)
+#define IOAPIC_RW_BITS (~(uint64_t)IOAPIC_RO_BITS)
+
#define IOAPIC_TRIGGER_EDGE 0
#define IOAPIC_TRIGGER_LEVEL 1
--
1.8.3.1
- [Qemu-devel] [PULL 00/24] Misc patches for 2016-05-23, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 03/24] i386: kvmvapic: initialise imm32 variable, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 06/24] ioapic: keep RO bits for IOAPIC entry,
Paolo Bonzini <=
- [Qemu-devel] [PULL 05/24] target-i386: key sfence availability on CPUID_SSE, not CPUID_SSE2, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 09/24] memory: drop find_ram_block(), Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 08/24] vl: change runstate only if new state is different from current state, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 13/24] memory: remove unnecessary masking of MemoryRegion ram_addr, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 07/24] ioapic: clear remote irr bit for edge-triggered interrupts, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 01/24] exec.c: Ensure right alignment also for file backed ram, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 02/24] docs/atomics.txt: Update pointer to linux macro, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 10/24] exec: adjust rcu_read_lock requirement, Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 18/24] esp: check command buffer length before write(CVE-2016-4439), Paolo Bonzini, 2016/05/23
- [Qemu-devel] [PULL 04/24] configure: Allow builds with extra warnings, Paolo Bonzini, 2016/05/23