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[Qemu-devel] [PATCH 21/23] hw/intc/arm_gicv3: Work around Linux assuming
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 21/23] hw/intc/arm_gicv3: Work around Linux assuming interrupts are group 1 |
Date: |
Mon, 9 May 2016 18:29:47 +0100 |
The Linux kernel's GICv3 driver assumes that all interrupts are in
group 1. This is correct if the system supports the Security extensions,
because in that case the kernel cannot configure the interrupts and
it must have been done already by firmware. However if the system does
not support the Security extensions then the kernel is perfectly capable
of configuring them into group 1 itself if it wants them there; it
just doesn't.
Work around this by having the GICv3 emulation put all the interrupts
into group 1 if we're directly booting a Linux kernel, whether the
Security extensions are supported or not.
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gicv3_common.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c
index 901ec60..73d3c6d 100644
--- a/hw/intc/arm_gicv3_common.c
+++ b/hw/intc/arm_gicv3_common.c
@@ -288,6 +288,13 @@ static void arm_gic_common_linux_init(ARMLinuxBootIf *obj,
* equivalent).
*/
s->irq_reset_nonsecure = true;
+ } else {
+ /* This is purely a workaround for broken Linux kernel behaviour
+ * on non-TrustZone systems. It assumes that interrupts have been
+ * set to group 1 even though it could do that itself for a non-secure
+ * GIC.
+ */
+ s->irq_reset_nonsecure = true;
}
}
--
1.9.1
- [Qemu-devel] [PATCH 00/23] GICv3 emulation, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 21/23] hw/intc/arm_gicv3: Work around Linux assuming interrupts are group 1,
Peter Maydell <=
- [Qemu-devel] [PATCH 22/23] NOT-FOR-UPSTREAM: kernel: Add definitions for GICv3 attributes, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 20/23] target-arm/monitor.c: Advertise emulated GICv3 in capabilities, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 16/23] hw/intc/arm_gicv3: Implement gicv3_cpuif_update(), Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 19/23] target-arm/machine.c: Allow user to request GICv3 emulation, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 02/23] bitops.h: Implement half-shuffle and half-unshuffle ops, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 05/23] target-arm: Add mp-affinity property for ARM CPU class, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 04/23] target-arm: Provide hook to tell GICv3 about changes of security state, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 18/23] hw/intc/arm_gicv3: Add IRQ handling CPU interface registers, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 07/23] hw/intc/arm_gicv3: Move irq lines into GICv3CPUState structure, Peter Maydell, 2016/05/09
- [Qemu-devel] [PATCH 10/23] hw/intc/arm_gicv3: Implement functions to identify next pending irq, Peter Maydell, 2016/05/09