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[Qemu-devel] [PATCH 40/52] target-m68k: add exg ops
From: |
Laurent Vivier |
Subject: |
[Qemu-devel] [PATCH 40/52] target-m68k: add exg ops |
Date: |
Wed, 4 May 2016 23:20:57 +0200 |
Signed-off-by: Laurent Vivier <address@hidden>
---
target-m68k/translate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 53c3c41..df5ce94 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -2721,6 +2721,45 @@ DISAS_INSN(eor)
DEST_EA(env, insn, OS_LONG, dest, &addr);
}
+DISAS_INSN(exg)
+{
+ TCGv src;
+ TCGv reg;
+ TCGv dest;
+ int exg_mode;
+
+ exg_mode = insn & 0x1f8;
+
+ dest = tcg_temp_new();
+ switch (exg_mode) {
+ case 0x140:
+ /* exchange Dx and Dy */
+ src = DREG(insn, 9);
+ reg = DREG(insn, 0);
+ tcg_gen_mov_i32(dest, src);
+ tcg_gen_mov_i32(src, reg);
+ tcg_gen_mov_i32(reg, dest);
+ break;
+ case 0x148:
+ /* exchange Ax and Ay */
+ src = AREG(insn, 9);
+ reg = AREG(insn, 0);
+ tcg_gen_mov_i32(dest, src);
+ tcg_gen_mov_i32(src, reg);
+ tcg_gen_mov_i32(reg, dest);
+ break;
+ case 0x188:
+ /* exchange Dx and Ay */
+ src = DREG(insn, 9);
+ reg = AREG(insn, 0);
+ tcg_gen_mov_i32(dest, src);
+ tcg_gen_mov_i32(src, reg);
+ tcg_gen_mov_i32(reg, dest);
+ break;
+ }
+ tcg_temp_free(dest);
+}
+
DISAS_INSN(and)
{
TCGv src;
@@ -4785,6 +4824,12 @@ void register_m68k_insns (CPUM68KState *env)
INSN(cmpa, b0c0, f0c0, M68000);
INSN(eor, b180, f1c0, CF_ISA_A);
BASE(and, c000, f000);
+ INSN(undef, c140, f1f8, CF_ISA_A);
+ INSN(exg, c140, f1f8, M68000);
+ INSN(undef, c148, f1f8, CF_ISA_A);
+ INSN(exg, c148, f1f8, M68000);
+ INSN(undef, c188, f1f8, CF_ISA_A);
+ INSN(exg, c188, f1f8, M68000);
BASE(mulw, c0c0, f0c0);
INSN(abcd_reg, c100, f1f8, M68000);
INSN(abcd_mem, c108, f1f8, M68000);
--
2.5.5
- Re: [Qemu-devel] [PATCH 35/52] target-m68k: inline rotate ops, (continued)
- [Qemu-devel] [PATCH 36/52] target-m68k: inline shift ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 37/52] target-m68k: add cas/cas2 ops, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 38/52] target-m68k: add linkl, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 39/52] target-m68k: movem, Laurent Vivier, 2016/05/04
- Re: [Qemu-devel] [PATCH 33/52] target-m68k: inline divu/divs, Richard Henderson, 2016/05/06
- [Qemu-devel] [PATCH 40/52] target-m68k: add exg ops,
Laurent Vivier <=
- [Qemu-devel] [PATCH 41/52] target-m68k: add addressing modes to not, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 44/52] target-m68k: and can manage word and byte operands, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 42/52] target-m68k: eor can manage word and byte operands, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 45/52] target-m68k: suba/adda can manage word operand, Laurent Vivier, 2016/05/04
- [Qemu-devel] [PATCH 46/52] target-m68k: introduce byte and word cc_ops, Laurent Vivier, 2016/05/04