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[Qemu-devel] [PATCH v3 6/7] target-arm/translate-a64.c: Unify some of th
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v3 6/7] target-arm/translate-a64.c: Unify some of the ldst_reg decoding |
Date: |
Fri, 29 Apr 2016 14:08:03 +0200 |
From: "Edgar E. Iglesias" <address@hidden>
The various load/store variants under disas_ldst_reg can all reuse the
same decoding for opc, size, rt and is_vector.
This patch unifies the decoding in preparation for generating
instruction syndromes for data aborts.
This will allow us to reduce the number of places to hook in updates
to the load/store state needed to generate the insn syndromes.
No functional change.
Reviewed-by: Sergey Fedorov <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/translate-a64.c | 41 +++++++++++++++++++++++------------------
1 file changed, 23 insertions(+), 18 deletions(-)
diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 5c8dddb..24f5e17 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -2086,19 +2086,19 @@ static void disas_ldst_pair(DisasContext *s, uint32_t
insn)
* size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit
* opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32
*/
-static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn)
+static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn,
+ int opc,
+ int size,
+ int rt,
+ bool is_vector)
{
- int rt = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int imm9 = sextract32(insn, 12, 9);
- int opc = extract32(insn, 22, 2);
- int size = extract32(insn, 30, 2);
int idx = extract32(insn, 10, 2);
bool is_signed = false;
bool is_store = false;
bool is_extended = false;
bool is_unpriv = (idx == 2);
- bool is_vector = extract32(insn, 26, 1);
bool post_index;
bool writeback;
@@ -2205,19 +2205,19 @@ static void disas_ldst_reg_imm9(DisasContext *s,
uint32_t insn)
* Rn: address register or SP for base
* Rm: offset register or ZR for offset
*/
-static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn)
+static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn,
+ int opc,
+ int size,
+ int rt,
+ bool is_vector)
{
- int rt = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
int shift = extract32(insn, 12, 1);
int rm = extract32(insn, 16, 5);
- int opc = extract32(insn, 22, 2);
int opt = extract32(insn, 13, 3);
- int size = extract32(insn, 30, 2);
bool is_signed = false;
bool is_store = false;
bool is_extended = false;
- bool is_vector = extract32(insn, 26, 1);
TCGv_i64 tcg_rm;
TCGv_i64 tcg_addr;
@@ -2294,14 +2294,14 @@ static void disas_ldst_reg_roffset(DisasContext *s,
uint32_t insn)
* Rn: base address register (inc SP)
* Rt: target register
*/
-static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn)
+static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn,
+ int opc,
+ int size,
+ int rt,
+ bool is_vector)
{
- int rt = extract32(insn, 0, 5);
int rn = extract32(insn, 5, 5);
unsigned int imm12 = extract32(insn, 10, 12);
- bool is_vector = extract32(insn, 26, 1);
- int size = extract32(insn, 30, 2);
- int opc = extract32(insn, 22, 2);
unsigned int offset;
TCGv_i64 tcg_addr;
@@ -2360,20 +2360,25 @@ static void disas_ldst_reg_unsigned_imm(DisasContext
*s, uint32_t insn)
/* Load/store register (all forms) */
static void disas_ldst_reg(DisasContext *s, uint32_t insn)
{
+ int rt = extract32(insn, 0, 5);
+ int opc = extract32(insn, 22, 2);
+ bool is_vector = extract32(insn, 26, 1);
+ int size = extract32(insn, 30, 2);
+
switch (extract32(insn, 24, 2)) {
case 0:
if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) {
- disas_ldst_reg_roffset(s, insn);
+ disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector);
} else {
/* Load/store register (unscaled immediate)
* Load/store immediate pre/post-indexed
* Load/store register unprivileged
*/
- disas_ldst_reg_imm9(s, insn);
+ disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector);
}
break;
case 1:
- disas_ldst_reg_unsigned_imm(s, insn);
+ disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector);
break;
default:
unallocated_encoding(s);
--
2.5.0
- [Qemu-devel] [PATCH v3 0/7] arm: Steps towards EL2 support round 6, Edgar E. Iglesias, 2016/04/29
- [Qemu-devel] [PATCH v3 2/7] gen-icount: Use tcg_set_insn_param, Edgar E. Iglesias, 2016/04/29
- [Qemu-devel] [PATCH v3 1/7] tcg: Add tcg_set_insn_param, Edgar E. Iglesias, 2016/04/29
- [Qemu-devel] [PATCH v3 5/7] target-arm/translate-a64.c: Use extract32 in disas_ldst_reg_imm9, Edgar E. Iglesias, 2016/04/29
- [Qemu-devel] [PATCH v3 6/7] target-arm/translate-a64.c: Unify some of the ldst_reg decoding,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v3 7/7] target-arm: A64: Create Instruction Syndromes for Data Aborts, Edgar E. Iglesias, 2016/04/29
- [Qemu-devel] [PATCH v3 4/7] target-arm: Split data abort syndrome generator, Edgar E. Iglesias, 2016/04/29
- [Qemu-devel] [PATCH v3 3/7] target-arm: Add the IL flag to syn_data_abort, Edgar E. Iglesias, 2016/04/29