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[Qemu-devel] [PATCH v4 02/16] intel_iommu: allow queued invalidation for
From: |
Peter Xu |
Subject: |
[Qemu-devel] [PATCH v4 02/16] intel_iommu: allow queued invalidation for IR |
Date: |
Tue, 19 Apr 2016 16:38:28 +0800 |
Queued invalidation is required for IR. This patch add basic support for
interrupt cache invalidate requests. Since we currently have no IR cache
implemented yet, we can just skip all interrupt cache invalidation
requests for now.
Signed-off-by: Peter Xu <address@hidden>
---
hw/i386/intel_iommu.c | 9 +++++++++
hw/i386/intel_iommu_internal.h | 2 ++
2 files changed, 11 insertions(+)
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 347718f..4b0558e 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -1400,6 +1400,15 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s)
}
break;
+ case VTD_INV_DESC_IEC:
+ VTD_DPRINTF(INV, "Interrupt Entry Cache Invalidation "
+ "not implemented yet");
+ /*
+ * Since currently we do not cache interrupt entries, we can
+ * just mark this descriptor as "good" and move on.
+ */
+ break;
+
default:
VTD_DPRINTF(GENERAL, "error: unkonw Invalidation Descriptor type "
"hi 0x%"PRIx64 " lo 0x%"PRIx64 " type %"PRIu8,
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index e5f514c..b648e69 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -286,6 +286,8 @@ typedef struct VTDInvDesc VTDInvDesc;
#define VTD_INV_DESC_TYPE 0xf
#define VTD_INV_DESC_CC 0x1 /* Context-cache Invalidate Desc */
#define VTD_INV_DESC_IOTLB 0x2
+#define VTD_INV_DESC_IEC 0x4 /* Interrupt Entry Cache
+ Invalidate Descriptor */
#define VTD_INV_DESC_WAIT 0x5 /* Invalidation Wait Descriptor */
#define VTD_INV_DESC_NONE 0 /* Not an Invalidate Descriptor */
--
2.4.3
- [Qemu-devel] [PATCH v4 00/16] IOMMU: Enable interrupt remapping for Intel IOMMU, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 01/16] acpi: enable INTR for DMAR report structure, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 02/16] intel_iommu: allow queued invalidation for IR,
Peter Xu <=
- [Qemu-devel] [PATCH v4 03/16] intel_iommu: set IR bit for ECAP register, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 04/16] acpi: add DMAR scope definition for root IOAPIC, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 05/16] intel_iommu: define interrupt remap table addr register, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 06/16] intel_iommu: handle interrupt remap enable, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 08/16] intel_iommu: provide helper function vtd_get_iommu, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 07/16] intel_iommu: define several structs for IOMMU IR, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 09/16] intel_iommu: add IR translation faults defines, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 10/16] intel_iommu: Add support for PCI MSI remap, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 12/16] ioapic: introduce ioapic_entry_parse() helper, Peter Xu, 2016/04/19
- [Qemu-devel] [PATCH v4 11/16] q35: ioapic: add support for emulated IOAPIC IR, Peter Xu, 2016/04/19