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[Qemu-devel] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs |
Date: |
Thu, 24 Mar 2016 15:30:54 +1100 |
From: Benjamin Herrenschmidt <address@hidden>
Signed-off-by: Benjamin Herrenschmidt <address@hidden>
[clg: squashed in patch 'ppc: Add dummy ACOP SPR' ]
Signed-off-by: Cédric Le Goater <address@hidden>
Reviewed-by: Thomas Huth <address@hidden>
Reviewed-by: David Gibson <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target-ppc/cpu.h | 3 +++
target-ppc/translate_init.c | 12 ++++++++++++
2 files changed, 15 insertions(+)
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h
index 29c4860..676081e 100644
--- a/target-ppc/cpu.h
+++ b/target-ppc/cpu.h
@@ -1355,7 +1355,9 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
ifetch)
#define SPR_SRR1 (0x01B)
#define SPR_CFAR (0x01C)
#define SPR_AMR (0x01D)
+#define SPR_ACOP (0x01F)
#define SPR_BOOKE_PID (0x030)
+#define SPR_BOOKS_PID (0x030)
#define SPR_BOOKE_DECAR (0x036)
#define SPR_BOOKE_CSRR0 (0x03A)
#define SPR_BOOKE_CSRR1 (0x03B)
@@ -1706,6 +1708,7 @@ static inline int cpu_mmu_index (CPUPPCState *env, bool
ifetch)
#define SPR_POWER_SPMC1 (0x37C)
#define SPR_POWER_SPMC2 (0x37D)
#define SPR_POWER_MMCRS (0x37E)
+#define SPR_WORT (0x37F)
#define SPR_PPR (0x380)
#define SPR_750_GQR0 (0x390)
#define SPR_440_DNV0 (0x390)
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c
index 37c4fb5..5cec1df 100644
--- a/target-ppc/translate_init.c
+++ b/target-ppc/translate_init.c
@@ -8018,6 +8018,18 @@ static void gen_spr_power8_ic(CPUPPCState *env)
&spr_read_generic, SPR_NOACCESS,
&spr_read_generic, &spr_write_generic,
0);
+ spr_register_kvm(env, SPR_ACOP, "ACOP",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_ACOP, 0);
+ spr_register_kvm(env, SPR_BOOKS_PID, "PID",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_PID, 0);
+ spr_register_kvm(env, SPR_WORT, "WORT",
+ SPR_NOACCESS, SPR_NOACCESS,
+ &spr_read_generic, &spr_write_generic,
+ KVM_REG_PPC_WORT, 0);
#endif
}
--
2.5.5
- [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 05/16] ppc: Add a bunch of hypervisor SPRs to Book3s, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 01/16] ppc64: set MSR_SF bit, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 04/16] ppc: Add macros to register hypervisor mode SPRs, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 14/16] hw/net/spapr_llan: Fix receive buffer handling for better performance, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 08/16] ppc: Initialize AMOR in PAPR mode, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 11/16] ppc: Add dummy CIABR SPR, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 15/16] hw/net/spapr_llan: Enable the RX buffer pools by default for new machines, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 06/16] ppc: Create cpu_ppc_set_papr() helper, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 07/16] ppc: Add dummy SPR_IC for POWER8, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 12/16] ppc: A couple more dummy POWER8 Book4 regs,
David Gibson <=
- [Qemu-devel] [PULL 02/16] spapr/target-ppc/kvm: Only add hcall-instructions if KVM supports it, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 03/16] ppc: Update SPR definitions, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 13/16] hw/net/spapr_llan: Extract rx buffer code into separate functions, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 09/16] ppc: Fix writing to AMR/UAMOR, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 10/16] ppc: Add POWER8 IAMR register, David Gibson, 2016/03/24
- [Qemu-devel] [PULL 16/16] ppc: move POWER8 Book4 regs in their own routine, David Gibson, 2016/03/24
- Re: [Qemu-devel] [PULL 00/16] ppc-for-2.6 queue 20160324, Peter Maydell, 2016/03/24