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Re: [Qemu-devel] [PATCH] ppc64: set MSR_SF bit

From: Alexander Graf
Subject: Re: [Qemu-devel] [PATCH] ppc64: set MSR_SF bit
Date: Wed, 16 Mar 2016 11:42:29 +0100
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.11; rv:38.0) Gecko/20100101 Thunderbird/38.6.0

On 16.03.16 11:32, Thomas Huth wrote:
> On 16.03.2016 11:06, Alexander Graf wrote:
>> On 16.03.16 11:05, Laurent Vivier wrote:
>>> On 16/03/2016 10:48, Alexander Graf wrote:
>>>> On 16.03.16 10:43, Laurent Vivier wrote:
>>>>> When a qemu-system-ppc64 is started, the 64-bit mode bit
>>>>> is not set in MSR.
>>>>> Signed-off-by: Laurent Vivier <address@hidden>
>>>> I guess commit 2cf3eb6df552cee74b52de9989e270b74e42847e broke this. I'm
>>>> surprised it didn't cause us more problems :).
>>> Linux kernel is ready to manage that: see enable_64b_mode in
>>> arch/powerpc/kernel/head_64.S
>> We don't boot Linux directly though, only openBIOS and SLOF :).
> Both, SLOF and OpenBIOS, seem to enable the SF bit manually, too, see:
> https://github.com/qemu/openbios/blob/master/arch/ppc/qemu/start.S#L524
> https://github.com/aik/SLOF/blob/master/board-qemu/llfw/startup.S#L91

Power up is slightly tricky, as machine state is pushed into the CPU
from the outside FWIW. I think we're "cleanest" if we just consider
power up a reset.

Reset is properly defined as an exception (0x100). For exceptions, the
970MP user manual for example says:

4.5 Exception Definitions
When an exception/interrupt is taken, all bits in the MSR are set to
‘0’, with the following exceptions:
• Exceptions always set MSR[SF] to ‘1’.

So the qemu fix is the correct one IMHO.


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