[Top][All Lists]

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing

From: Cédric Le Goater
Subject: [Qemu-devel] [PATCH 00/17] ppc: preparing pnv landing
Date: Mon, 14 Mar 2016 17:56:23 +0100


This is a first mini-serie of patches adding support for new ppc SPRs.
They were taken from Ben's larger patchset adding the ppc powernv
platform and they should already be useful for the pseries guest

Initial patches come from :


The changes are mostly due to the rebase on Dave's 2.6 branch:


A couple more are bisect and checkpatch fixes and finally some patches
were merge to reduce the noise.


The patchset is also available here: 


It was quickly tested with a pseries guest using KVM and TCG.



Benjamin Herrenschmidt (17):
  ppc: Update SPR definitions
  ppc: Add macros to register hypervisor mode SPRs
  ppc: Add a bunch of hypervisor SPRs to Book3s
  ppc: Add number of threads per core to the processor definition
  ppc: Fix hreg_store_msr() so that non-HV mode cannot alter MSR:HV
  ppc: Create cpu_ppc_set_papr() helper
  ppc: Better figure out if processor has HV mode
  ppc: Add placeholder SPRs for DPDES and DHDES on P8
  ppc: SPURR & PURR are HV writeable and privileged
  ppc: Add dummy SPR_IC for POWER8
  ppc: Initialize AMOR in PAPR mode
  ppc: Fix writing to AMR/UAMOR
  ppc: Add POWER8 IAMR register
  ppc: Add dummy write to VTB
  ppc: Add dummy POWER8 MPPR register
  ppc: Add dummy CIABR SPR
  ppc: A couple more dummy POWER8 Book4 regs

 hw/ppc/spapr.c              |  11 +-
 target-ppc/cpu-qom.h        |   1 +
 target-ppc/cpu.h            |  68 ++++++-
 target-ppc/excp_helper.c    |   8 +-
 target-ppc/helper_regs.h    |   4 +-
 target-ppc/translate.c      |  30 +--
 target-ppc/translate_init.c | 461 ++++++++++++++++++++++++++++++++++++++++----
 7 files changed, 510 insertions(+), 73 deletions(-)


reply via email to

[Prev in Thread] Current Thread [Next in Thread]