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[Qemu-devel] [PULL 10/20] target-arm: Make mode switches from Hyp via CP
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/20] target-arm: Make mode switches from Hyp via CPS and MRS illegal |
Date: |
Fri, 26 Feb 2016 15:20:15 +0000 |
Mode switches from Hyp to any other mode via the CPS and MRS
instructions are illegal mode switches (though obviously switching
via exception return is valid). Add this check to bad_mode_switch().
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Sergey Fedorov <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ff5f895..24ea48e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5200,12 +5200,20 @@ void arm_cp_reset_ignore(CPUARMState *env, const
ARMCPRegInfo *opaque)
/* Helper coprocessor reset function for do-nothing-on-reset registers */
}
-static int bad_mode_switch(CPUARMState *env, int mode)
+static int bad_mode_switch(CPUARMState *env, int mode, CPSRWriteType
write_type)
{
/* Return true if it is not valid for us to switch to
* this CPU mode (ie all the UNPREDICTABLE cases in
* the ARM ARM CPSRWriteByInstr pseudocode).
*/
+
+ /* Changes to or from Hyp via MSR and CPS are illegal. */
+ if (write_type == CPSRWriteByInstr &&
+ ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_HYP ||
+ mode == ARM_CPU_MODE_HYP)) {
+ return 1;
+ }
+
switch (mode) {
case ARM_CPU_MODE_USR:
case ARM_CPU_MODE_SYS:
@@ -5324,7 +5332,7 @@ void cpsr_write(CPUARMState *env, uint32_t val, uint32_t
mask,
if (write_type != CPSRWriteRaw &&
(env->uncached_cpsr & CPSR_M) != CPSR_USER &&
((env->uncached_cpsr ^ val) & mask & CPSR_M)) {
- if (bad_mode_switch(env, val & CPSR_M)) {
+ if (bad_mode_switch(env, val & CPSR_M, write_type)) {
/* Attempt to switch to an invalid mode: this is UNPREDICTABLE in
* v7, and has defined behaviour in v8:
* + leave CPSR.M untouched
--
1.9.1
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 06/20] target-arm: Add comment about not implementing NSACR.RFR, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 01/20] target-arm: Give CPSR setting on 32-bit exception return its own helper, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 03/20] target-arm: Raw CPSR writes should skip checks and bank switching, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 10/20] target-arm: Make mode switches from Hyp via CPS and MRS illegal,
Peter Maydell <=
- [Qemu-devel] [PULL 05/20] target-arm: In cpsr_write() ignore mode switches from User mode, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 08/20] target-arm: Forbid mode switch to Mon from Secure EL1, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 02/20] target-arm: Add write_type argument to cpsr_write(), Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 17/20] sdhci: Revert "add optional quirk property to disable card insertion/removal interrupts", Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 12/20] target-arm: Fix handling of SDCR for 32-bit code, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 04/20] linux-user: Use restrictive mask when calling cpsr_write(), Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 11/20] target-arm: Make Monitor->NS PL1 mode changes illegal if HCR.TGE is 1, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 20/20] target-arm: Make reserved ranges in ID_AA64* spaces RAZ, not UNDEF, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 13/20] target-arm: Implement MDCR_EL3.TPM and MDCR_EL2.TPM traps, Peter Maydell, 2016/02/26
- [Qemu-devel] [PULL 14/20] ARM: PL061: Checking register r/w accesses to reserved area, Peter Maydell, 2016/02/26