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From: | Jean-Christophe DUBOIS |
Subject: | Re: [Qemu-devel] [PATCH v2 7/9] i.MX: Add i.MX6 SOC implementation. |
Date: | Thu, 18 Feb 2016 21:51:38 +0100 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 |
Le 16/02/2016 22:57, Peter Maydell a
écrit :
On 16 February 2016 at 21:47, Jean-Christophe DUBOIS <address@hidden> wrote:In QEMU, other Cortex A9 (Versatilepb.c, Exynos, Zynq ...) are also setting has_el3 to false ...So these generally are the "legacy" platforms which were added before we ever had EL3 support in QEMU. For them it's hard to turn the EL3 support on for the board even if in theory it ought to be on, because we don't know what users are running on it that we might break. With a new to QEMU board we have an opportunity to get it right from the start. OK, so is the "highbank" the only Qemu Cortex A9 board supporting el3 yet? -kernel I would expect to work, though, at least if the only issue is the interrupt controller setup. It seems worth investigating why it goes wrong. Well, I can boot uniprocessor (-smp 1) without trouble but if I turn logs on (guest_errors,unimp) I am getting a lot of
I am not sure if this is a problem. Do you have some opinion on
this? JC thanks -- PMM |
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