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[Qemu-devel] [PULL 03/15] target-arm: Use access_trap_aa32s_el1() for SC
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/15] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR |
Date: |
Tue, 9 Feb 2016 18:42:53 +0000 |
The registers MVBAR and SCR should have the behaviour of trapping to
EL3 if accessed from Secure EL1, but we were incorrectly implementing
them to UNDEF (which would trap to EL1). Fix this by using the new
access_trap_aa32s_el1() access function.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 1efe304..98eccd6 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3548,7 +3548,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.resetvalue = 0, .writefn = scr_write },
{ .name = "SCR", .type = ARM_CP_ALIAS,
.cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0,
- .access = PL3_RW, .fieldoffset = offsetoflow32(CPUARMState,
cp15.scr_el3),
+ .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3),
.writefn = scr_write },
{ .name = "MDCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 3, .opc2 = 1,
@@ -3571,7 +3572,8 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
.access = PL3_W | PL1_R, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.nsacr) },
{ .name = "MVBAR", .cp = 15, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 1,
- .access = PL3_RW, .writefn = vbar_write, .resetvalue = 0,
+ .access = PL1_RW, .accessfn = access_trap_aa32s_el1,
+ .writefn = vbar_write, .resetvalue = 0,
.fieldoffset = offsetof(CPUARMState, cp15.mvbar) },
{ .name = "SCTLR_EL3", .state = ARM_CP_STATE_AA64,
.type = ARM_CP_ALIAS, /* reset handled by AArch32 view */
--
1.9.1
- [Qemu-devel] [PULL 00/15] target-arm queue, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 13/15] sd: limit 'req.cmd' while using as an array index, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 14/15] hw/arm/virt: fix max-cpus check, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 15/15] bcm2835_property: implement "get board revision" query, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 09/15] target-arm: Fix IL bit reported for Thumb coprocessor traps, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 10/15] target-arm: Fix IL bit reported for Thumb VFP and Neon traps, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 03/15] target-arm: Use access_trap_aa32s_el1() for SCR and MVBAR,
Peter Maydell <=
- [Qemu-devel] [PULL 07/15] target-arm: Enable EL3 for Cortex-A53 and Cortex-A57, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 12/15] target-arm: Implement checking of fired watchpoint, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 11/15] cpu: Add callback to check architectural watchpoint match, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 08/15] target-arm: Correct misleading 'is_thumb' syn_* parameter names, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 02/15] target-arm: Implement MDCR_EL3 and SDCR, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 01/15] target-arm: Fix typo in comment in arm_is_secure_below_el3(), Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 04/15] target-arm: Update arm_generate_debug_exceptions() to handle EL2/EL3, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 06/15] target-arm: Implement NSACR trapping behaviour, Peter Maydell, 2016/02/09
- [Qemu-devel] [PULL 05/15] target-arm: Add isread parameter to CPAccessFns, Peter Maydell, 2016/02/09
- Re: [Qemu-devel] [PULL 00/15] target-arm queue, Peter Maydell, 2016/02/11