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[Qemu-devel] [PATCH v2 4/5] target-arm: Add PMUSERENR_EL0 register
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v2 4/5] target-arm: Add PMUSERENR_EL0 register |
Date: |
Fri, 5 Feb 2016 16:55:23 -0800 |
The Linux kernel accesses this register early in its setup.
Signed-off-by: Christopher Covington <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
---
target-arm/helper.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 8d401c6..b4bf6fa 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1094,6 +1094,12 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
.fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
.resetvalue = 0,
.writefn = pmuserenr_write, .raw_writefn = raw_write },
+ { .name = "PMUSERENR_EL0", .state = ARM_CP_STATE_AA64,
+ .opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 0,
+ .access = PL0_R | PL1_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
+ .resetvalue = 0,
+ .writefn = pmuserenr_write, .raw_writefn = raw_write },
{ .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 =
1,
.access = PL1_RW,
.fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
--
2.5.0
[Qemu-devel] [PATCH v2 2/5] target-arm: Add Some of the performance monitor registers, Alistair Francis, 2016/02/05
[Qemu-devel] [PATCH v2 3/5] target-arm: Add the pmovsclr_el0 and pmintenclr_el1 registers, Alistair Francis, 2016/02/05
[Qemu-devel] [PATCH v2 4/5] target-arm: Add PMUSERENR_EL0 register,
Alistair Francis <=
[Qemu-devel] [PATCH v2 5/5] target-arm: Unmask PMU bits in debug feature register, Alistair Francis, 2016/02/05