Re: [Qemu-devel] [PATCH RFC 0/4] ARM SMMUv3 Emulation

[Alistair Francis]

On Fri, Jan 15, 2016 at 9:28 AM, Peter Maydell <address@hidden> wrote:
> On 11 January 2016 at 14:16,  <address@hidden> wrote:
>> From: Prem Mallappa <address@hidden>
>>
>> Implementation Notes:
>>
>>         - SMMUv3 model, as per ARM SMMUv3 11.0 spec
>>         - Works with Linux Kernel 4.4 SMMUv3 Driver By Will Deacon.
>>         - Stage1 only
>>         - only LPAE Translation tables supported
>>         - BE for translation tables is not supported.
>>         - Save/Restore not supported "YET".
>>         - Broadcom variant added, not much different at the moment
>>
>> Untested
>>         - Stage2 only
>>         - Stage1+Stage2 support
>>
>> Future planned work:
>>         - MSI(x) support
>
> So, Xilinx also has an SMMU model (out of tree). Edgar, Alistair,
> would you care to have a look at this code and suggest whether one
> or the other is a better base to start from? (If there's not much
> difference then I'm inclined to start with the one that got posted
> to the list first :-))

Edgar has done all of the SMMU work for Xilinx, he knows it the best.
I'll let him comment on it.

For anyone interested you can see our implementation at:
https://github.com/Xilinx/qemu/blob/master/hw/misc/arm-smmu.c. It does
use the register API that we have been trying to upstream.

Thanks,

Alistair

>
> thanks
> -- PMM
>