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[Qemu-devel] [RFC 8/9] target-ppc: Helper to determine page size informa
From: |
David Gibson |
Subject: |
[Qemu-devel] [RFC 8/9] target-ppc: Helper to determine page size information from hpte alone |
Date: |
Fri, 15 Jan 2016 18:04:39 +1100 |
h_enter() in the spapr code needs to know the page size of the HPTE it's
about to insert. Unlike other paths that do this, it doesn't have access
to the SLB, so at the moment it determines this with some open-coded
tests which assume POWER7 or POWER8 page size encodings.
To make this more flexible add ppc_hash64_hpte_page_shift_noslb() to
determine both the "base" page size per segment, and the individual
effective page size from an HPTE alone.
This means that the spapr code should now be able to handle any page size
listed in the env->sps table.
Signed-off-by: David Gibson <address@hidden>
---
hw/ppc/spapr_hcall.c | 25 ++++++-------------------
target-ppc/mmu-hash64.c | 37 ++++++++++++++++++++++++++++++++++++-
target-ppc/mmu-hash64.h | 3 +++
3 files changed, 45 insertions(+), 20 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index f7ca616..1a1bea8 100644
--- a/hw/ppc/spapr_hcall.c
+++ b/hw/ppc/spapr_hcall.c
@@ -57,31 +57,18 @@ static target_ulong h_enter(PowerPCCPU *cpu,
sPAPRMachineState *spapr,
target_ulong pte_index = args[1];
target_ulong pteh = args[2];
target_ulong ptel = args[3];
- target_ulong page_shift = 12;
+ unsigned apshift, spshift;
target_ulong raddr;
target_ulong index;
uint64_t token;
- /* only handle 4k and 16M pages for now */
- if (pteh & HPTE64_V_LARGE) {
-#if 0 /* We don't support 64k pages yet */
- if ((ptel & 0xf000) == 0x1000) {
- /* 64k page */
- } else
-#endif
- if ((ptel & 0xff000) == 0) {
- /* 16M page */
- page_shift = 24;
- /* lowest AVA bit must be 0 for 16M pages */
- if (pteh & 0x80) {
- return H_PARAMETER;
- }
- } else {
- return H_PARAMETER;
- }
+ apshift = ppc_hash64_hpte_page_shift_noslb(cpu, pteh, ptel, &spshift);
+ if (!apshift) {
+ /* Bad page size encoding */
+ return H_PARAMETER;
}
- raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << page_shift) - 1);
+ raddr = (ptel & HPTE64_R_RPN) & ~((1ULL << apshift) - 1);
if (raddr < machine->ram_size) {
/* Regular RAM - should have WIMG=0010 */
diff --git a/target-ppc/mmu-hash64.c b/target-ppc/mmu-hash64.c
index 38c1208..66f16d9 100644
--- a/target-ppc/mmu-hash64.c
+++ b/target-ppc/mmu-hash64.c
@@ -509,7 +509,7 @@ static unsigned hpte_page_shift(const struct
ppc_one_seg_page_size *sps,
mask = ((1ULL << ps->page_shift) - 1) & HPTE64_R_RPN;
- if ((pte1 & mask) == ps->pte_enc) {
+ if ((pte1 & mask) == (ps->pte_enc << HPTE64_R_RPN_SHIFT)) {
return ps->page_shift;
}
}
@@ -517,6 +517,41 @@ static unsigned hpte_page_shift(const struct
ppc_one_seg_page_size *sps,
return 0; /* Bad page size encoding */
}
+unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
+ uint64_t pte0, uint64_t pte1,
+ unsigned *seg_page_shift)
+{
+ CPUPPCState *env = &cpu->env;
+ int i;
+
+ if (!(pte0 & HPTE64_V_LARGE)) {
+ *seg_page_shift = 12;
+ return 12;
+ }
+
+ /*
+ * The encodings in env->sps need to be carefully chosen so that
+ * this gives an unambiguous result.
+ */
+ for (i = 0; i < PPC_PAGE_SIZES_MAX_SZ; i++) {
+ const struct ppc_one_seg_page_size *sps = &env->sps.sps[i];
+ unsigned shift;
+
+ if (!sps->page_shift) {
+ break;
+ }
+
+ shift = hpte_page_shift(sps, pte0, pte1);
+ if (shift) {
+ *seg_page_shift = sps->page_shift;
+ return shift;
+ }
+ }
+
+ *seg_page_shift = 0;
+ return 0;
+}
+
static hwaddr ppc_hash64_pte_raddr(PowerPCCPU *cpu, unsigned page_shift,
ppc_hash_pte64_t pte, target_ulong eaddr)
{
diff --git a/target-ppc/mmu-hash64.h b/target-ppc/mmu-hash64.h
index 8b19fb9..93d8fb6 100644
--- a/target-ppc/mmu-hash64.h
+++ b/target-ppc/mmu-hash64.h
@@ -15,6 +15,9 @@ void ppc_hash64_store_hpte(PowerPCCPU *cpu, target_ulong
index,
void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
target_ulong pte_index,
target_ulong pte0, target_ulong pte1);
+unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
+ uint64_t pte0, uint64_t pte1,
+ unsigned *seg_page_shift);
#endif
/*
--
2.5.0
- [Qemu-devel] [RFC 0/9] Clean up page size handling for ppc 64-bit hash MMUs with TCG, David Gibson, 2016/01/15
- [Qemu-devel] [RFC 7/9] target-ppc: Add new TLB invalidate by HPTE call for hash64 MMUs, David Gibson, 2016/01/15
- [Qemu-devel] [RFC 3/9] target-ppc: Rework SLB page size lookup, David Gibson, 2016/01/15
- [Qemu-devel] [RFC 5/9] target-ppc: Remove unused mmu models from ppc_tlb_invalidate_one, David Gibson, 2016/01/15
- [Qemu-devel] [RFC 1/9] target-ppc: Remove unused kvmppc_read_segment_page_sizes() stub, David Gibson, 2016/01/15
- [Qemu-devel] [RFC 6/9] target-ppc: Split 44x tlbiva from ppc_tlb_invalidate_one(), David Gibson, 2016/01/15
- [Qemu-devel] [RFC 9/9] target-ppc: Allow more page sizes for POWER7 & POWER8 in TCG, David Gibson, 2016/01/15
- [Qemu-devel] [RFC 8/9] target-ppc: Helper to determine page size information from hpte alone,
David Gibson <=
- [Qemu-devel] [RFC 4/9] target-ppc: Use actual page size encodings from HPTE, David Gibson, 2016/01/15
- [Qemu-devel] [RFC 2/9] target-ppc: Convert mmu-hash{32, 64}.[ch] from CPUPPCState to PowerPCCPU, David Gibson, 2016/01/15