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[Qemu-devel] [PULL v2 43/59] pc: acpi: q35: move IQCR() into SSDT
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v2 43/59] pc: acpi: q35: move IQCR() into SSDT |
Date: |
Sat, 9 Jan 2016 23:41:29 +0200 |
From: Igor Mammedov <address@hidden>
Signed-off-by: Igor Mammedov <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
hw/i386/acpi-build.c | 51 ++++++++++++++++++++++++++++++-----------------
hw/i386/q35-acpi-dsdt.dsl | 9 ---------
2 files changed, 33 insertions(+), 27 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index f0283f9..5bb544b 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -1525,6 +1525,36 @@ static Aml *build_gsi_link_dev(const char *name, uint8_t
uid, uint8_t gsi)
return dev;
}
+/* _CRS method - get current settings */
+static Aml *build_iqcr_method(bool is_piix4)
+{
+ Aml *if_ctx;
+ uint32_t irqs;
+ Aml *method = aml_method("IQCR", 1, AML_SERIALIZED);
+ Aml *crs = aml_resource_template();
+
+ irqs = 0;
+ aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
+ AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
+ aml_append(method, aml_name_decl("PRR0", crs));
+
+ aml_append(method,
+ aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
+
+ if (is_piix4) {
+ if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
+ aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
+ aml_append(method, if_ctx);
+ } else {
+ aml_append(method,
+ aml_store(aml_and(aml_arg(0), aml_int(0xF), NULL),
+ aml_name("PRRI")));
+ }
+
+ aml_append(method, aml_return(aml_name("PRR0")));
+ return method;
+}
+
static void build_piix4_pci0_int(Aml *table)
{
Aml *dev;
@@ -1556,24 +1586,7 @@ static void build_piix4_pci0_int(Aml *table)
}
aml_append(sb_scope, method);
- /* _CRS method - get current settings */
- method = aml_method("IQCR", 1, AML_SERIALIZED);
- {
- crs = aml_resource_template();
- irqs = 0;
- aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL,
- AML_ACTIVE_HIGH, AML_SHARED, &irqs, 1));
- aml_append(method, aml_name_decl("PRR0", crs));
-
- aml_append(method,
- aml_create_dword_field(aml_name("PRR0"), aml_int(5), "PRRI"));
-
- if_ctx = aml_if(aml_lless(aml_arg(0), aml_int(0x80)));
- aml_append(if_ctx, aml_store(aml_arg(0), aml_name("PRRI")));
- aml_append(method, if_ctx);
- aml_append(method, aml_return(aml_name("PRR0")));
- }
- aml_append(sb_scope, method);
+ aml_append(sb_scope, build_iqcr_method(true));
aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQ0")));
aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQ1")));
@@ -1619,6 +1632,8 @@ static void build_q35_pci0_int(Aml *table)
{
Aml *sb_scope = aml_scope("_SB");
+ aml_append(sb_scope, build_iqcr_method(false));
+
aml_append(sb_scope, build_link_dev("LNKA", 0, aml_name("PRQA")));
aml_append(sb_scope, build_link_dev("LNKB", 1, aml_name("PRQB")));
aml_append(sb_scope, build_link_dev("LNKC", 2, aml_name("PRQC")));
diff --git a/hw/i386/q35-acpi-dsdt.dsl b/hw/i386/q35-acpi-dsdt.dsl
index 2da3515..85b0a2c 100644
--- a/hw/i386/q35-acpi-dsdt.dsl
+++ b/hw/i386/q35-acpi-dsdt.dsl
@@ -305,15 +305,6 @@ DefinitionBlock (
}
Return (0x0B)
}
- Method(IQCR, 1, Serialized) {
- // _CRS method - get current settings
- Name(PRR0, ResourceTemplate() {
- Interrupt(, Level, ActiveHigh, Shared) { 0 }
- })
- CreateDWordField(PRR0, 0x05, PRRI)
- Store(And(Arg0, 0x0F), PRRI)
- Return (PRR0)
- }
External(LNKA, DeviceObj)
External(LNKB, DeviceObj)
--
MST
- [Qemu-devel] [PULL v2 33/59] pc: acpi: move PIIX4 isa-bridge and pm devices into SSDT, (continued)
- [Qemu-devel] [PULL v2 33/59] pc: acpi: move PIIX4 isa-bridge and pm devices into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 34/59] pc: acpi: move remaining GPE handlers into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 35/59] pc: acpi: pci: move link devices into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 36/59] pc: acpi: piix4: move IQCR() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 37/59] pc: acpi: piix4: move IQST() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 38/59] pc: acpi: piix4: move PCI0._PRT() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 39/59] pc: acpi: piix4: move remaining PCI hotplug bits into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 40/59] pc: acpi: piix4: acpi move PCI0 device to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 41/59] pc: acpi: q35: move GSI links to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 42/59] pc: acpi: q35: move link devices to SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 43/59] pc: acpi: q35: move IQCR() into SSDT,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v2 44/59] pc: acpi: q35: move IQST() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 46/59] pc: acpi: q35: move _PRT() into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 45/59] pc: acpi: q35: move ISA bridge into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 47/59] pc: acpi: q35: move PRTA routing table into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 49/59] pc: acpi: q35: move _PIC() method into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 48/59] pc: acpi: q35: move PRTP routing table into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 50/59] pc: acpi: q35: move PCI0._OSC() method into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 51/59] pc: acpi: q35: move PCI0 device definition into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 52/59] pc: acpi: q35: PCST, PCSB opregions and PCIB field into SSDT, Michael S. Tsirkin, 2016/01/09
- [Qemu-devel] [PULL v2 53/59] pc: acpi: switch to AML API composed DSDT, Michael S. Tsirkin, 2016/01/09