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Re: [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction transla


From: Paolo Bonzini
Subject: Re: [Qemu-devel] [RFC v6 00/14] Slow-path for atomic instruction translation
Date: Mon, 14 Dec 2015 10:33:23 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0


On 14/12/2015 09:41, Alvise Rigo wrote:
> In theory, the provided implementation of TCG LoadLink/StoreConditional
> can be used to properly handle atomic instructions on any architecture.

No, _in theory_ this implementation is wrong.  If a normal store can
make a concurrent LL-SC pair fail, it's provably _impossible_ to handle
LL/SC with a wait-free fast path for normal stores.

If we decide that it's "good enough", because the race is incredibly
rare and doesn't happen anyway for spinlocks, then fine.  But it should
be represented correctly in the commit messages.

Paolo



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