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Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/77] ppc: Use split I/D mmu modes t


From: Paolo Bonzini
Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 02/77] ppc: Use split I/D mmu modes to avoid flushes on interrupts
Date: Fri, 27 Nov 2015 13:15:31 +0100
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0


On 27/11/2015 11:29, Alexander Graf wrote:
> > We rework the way the MMU indices are calculated, providing separate
> > indices for I and D side based on MSR:IR and MSR:DR respectively,
> > and thus no longer need to flush the TLB on context changes. This also
> > adds correct support for HV as a separate address space.
> > 
> > Signed-off-by: Benjamin Herrenschmidt <address@hidden>
> 
> Paolo had a patch set poking at the same places a while back to speed up
> the ppc target by almost 10%.
> 
> Paolo, what happened to those patches? Would you prefer to rebase them
> on top of the HV bits or have Ben look into them while he's at it anyway? ;)

Ben decided to do it this way, which avoids a proliferation of MMU
modes.  The net effect of his patches is the same if not better.

Paolo



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