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[Qemu-devel] [PATCH v2 16/19] target-arm: Support multiple address space
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH v2 16/19] target-arm: Support multiple address spaces in page table walks |
Date: |
Mon, 16 Nov 2015 14:05:20 +0000 |
If we have a secure address space, use it in page table walks:
when doing the physical accesses to read descriptors, make them
through the correct address space.
(The descriptor reads are the only direct physical accesses
made in target-arm/ for CPUs which might have TrustZone.)
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/cpu.h | 9 +++++++++
target-arm/helper.c | 8 ++++++--
2 files changed, 15 insertions(+), 2 deletions(-)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ee873b7..5f81342 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -2003,6 +2003,15 @@ static inline int arm_asidx_from_attrs(CPUState *cs,
MemTxAttrs attrs)
{
return attrs.secure ? ARMASIdx_S : ARMASIdx_NS;
}
+
+/* Return the AddressSpace to use for a memory access
+ * (which depends on whether the access is S or NS, and whether
+ * the board gave us a separate AddressSpace for S accesses).
+ */
+static inline AddressSpace *arm_addressspace(CPUState *cs, MemTxAttrs attrs)
+{
+ return cpu_get_address_space(cs, arm_asidx_from_attrs(cs, attrs));
+}
#endif
#endif
diff --git a/target-arm/helper.c b/target-arm/helper.c
index ac388d1..415aa21 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6260,13 +6260,15 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr,
bool is_secure,
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
MemTxAttrs attrs = {};
+ AddressSpace *as;
attrs.secure = is_secure;
+ as = arm_addressspace(cs, attrs);
addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
if (fi->s1ptw) {
return 0;
}
- return address_space_ldl(cs->as, addr, attrs, NULL);
+ return address_space_ldl(as, addr, attrs, NULL);
}
static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure,
@@ -6276,13 +6278,15 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr,
bool is_secure,
ARMCPU *cpu = ARM_CPU(cs);
CPUARMState *env = &cpu->env;
MemTxAttrs attrs = {};
+ AddressSpace *as;
attrs.secure = is_secure;
+ as = arm_addressspace(cs, attrs);
addr = S1_ptw_translate(env, mmu_idx, addr, attrs, fsr, fi);
if (fi->s1ptw) {
return 0;
}
- return address_space_ldq(cs->as, addr, attrs, NULL);
+ return address_space_ldq(as, addr, attrs, NULL);
}
static bool get_phys_addr_v5(CPUARMState *env, uint32_t address,
--
1.9.1
- [Qemu-devel] [PATCH v2 17/19] hw/arm/virt: Wire up memory region to CPUs explicitly, (continued)
- [Qemu-devel] [PATCH v2 17/19] hw/arm/virt: Wire up memory region to CPUs explicitly, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 15/19] target-arm: Implement cpu_get_phys_page_attrs_debug, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 07/19] exec.c: Pass MemTxAttrs to iotlb_to_region so it uses the right AS, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 10/19] exec.c: Use correct AddressSpace in watch_mem_read and watch_mem_write, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 18/19] [RFC] hw/arm/virt: add secure memory region and UART, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 12/19] qom/cpu: Add MemoryRegion property, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 04/19] include/qom/cpu.h: Add new get_phys_page_attrs_debug method, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 13/19] target-arm: Add QOM property for Secure memory region, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 16/19] target-arm: Support multiple address spaces in page table walks,
Peter Maydell <=
- [Qemu-devel] [PATCH v2 02/19] exec.c: Allow target CPUs to define multiple AddressSpaces, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 19/19] HACK: rearrange the virt memory map to suit OP-TEE, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 06/19] cputlb.c: Use correct address space when looking up MemoryRegionSection, Peter Maydell, 2015/11/16
- [Qemu-devel] [PATCH v2 14/19] target-arm: Implement asidx_from_attrs, Peter Maydell, 2015/11/16