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[Qemu-devel] [PULL 15/27] target-arm: lpae: Make t0sz and t1sz signed in
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 15/27] target-arm: lpae: Make t0sz and t1sz signed integers |
Date: |
Tue, 27 Oct 2015 14:33:17 +0000 |
From: "Edgar E. Iglesias" <address@hidden>
Make t0sz and t1sz signed integers to match tsz and to make
it easier to implement support for AArch32 negative t0sz.
t1sz is changed for consistensy.
No functional change.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 7e35585..d07b4b7 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6535,12 +6535,12 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
*/
- uint32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
+ int32_t t0sz = extract32(tcr->raw_tcr, 0, 6);
if (va_size == 64) {
t0sz = MIN(t0sz, 39);
t0sz = MAX(t0sz, 16);
}
- uint32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
+ int32_t t1sz = extract32(tcr->raw_tcr, 16, 6);
if (va_size == 64) {
t1sz = MIN(t1sz, 39);
t1sz = MAX(t1sz, 16);
--
1.9.1
- [Qemu-devel] [PULL 24/27] target-arm: Add S2 translation to 64bit S1 PTWs, (continued)
- [Qemu-devel] [PULL 24/27] target-arm: Add S2 translation to 64bit S1 PTWs, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 16/27] target-arm: lpae: Move declaration of t0sz and t1sz, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 21/27] target-arm: Add support for S2 page-table protection bits, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 20/27] target-arm: Add computation of starting level for S2 PTW, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 01/27] target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked(), Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 07/27] i.MX: Standardize i.MX GPIO debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 10/27] i.MX: Standardize i.MX CCM debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 05/27] hw/arm/virt: don't use a15memmap directly, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 03/27] target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ), Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 04/27] arm_gic_kvm: Disable live migration if not supported, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 15/27] target-arm: lpae: Make t0sz and t1sz signed integers,
Peter Maydell <=
- [Qemu-devel] [PULL 12/27] i.MX: Standardize i.MX EPIT debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 18/27] target-arm: lpae: Replace tsz with computed inputsize, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 06/27] i.MX: Standardize i.MX serial debug., Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 22/27] target-arm: Avoid inline for get_phys_addr, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 08/27] i.MX: Standardize i.MX I2C debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 02/27] target-arm/translate.c: Handle non-executable page-straddling Thumb insns, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 09/27] i.MX: Standardize i.MX AVIC debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 11/27] i.MX: Standardize i.MX FEC debug, Peter Maydell, 2015/10/27
- [Qemu-devel] [PULL 27/27] target-arm: Add support for S1 + S2 MMU translations, Peter Maydell, 2015/10/27
- Re: [Qemu-devel] [PULL 00/27] target-arm queue, Peter Maydell, 2015/10/27