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[Qemu-devel] [PATCH v5 04/14] target-arm: Add support for AArch32 S2 neg
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH v5 04/14] target-arm: Add support for AArch32 S2 negative t0sz |
Date: |
Mon, 26 Oct 2015 14:01:57 +0100 |
From: "Edgar E. Iglesias" <address@hidden>
Add support for AArch32 S2 negative t0sz. In preparation for
using 40bit IPAs on AArch32.
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/helper.c | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4d8a25a..5e3d21e 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -6520,10 +6520,26 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
* This is a Non-secure PL0/1 stage 1 translation, so controlled by
* TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
*/
- t0sz = extract32(tcr->raw_tcr, 0, 6);
if (va_size == 64) {
+ /* AArch64 translation. */
+ t0sz = extract32(tcr->raw_tcr, 0, 6);
t0sz = MIN(t0sz, 39);
t0sz = MAX(t0sz, 16);
+ } else if (mmu_idx != ARMMMUIdx_S2NS) {
+ /* AArch32 stage 1 translation. */
+ t0sz = extract32(tcr->raw_tcr, 0, 3);
+ } else {
+ /* AArch32 stage 2 translation. */
+ bool sext = extract32(tcr->raw_tcr, 4, 1);
+ bool sign = extract32(tcr->raw_tcr, 3, 1);
+ t0sz = sextract32(tcr->raw_tcr, 0, 4);
+
+ /* If the sign-extend bit is not the same as t0sz[3], the result
+ * is unpredictable. Flag this as a guest error. */
+ if (sign != sext) {
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "AArch32: VTCR.S / VTCR.T0SZ[3] missmatch\n");
+ }
}
t1sz = extract32(tcr->raw_tcr, 16, 6);
if (va_size == 64) {
--
1.9.1
- [Qemu-devel] [PATCH v5 00/14] arm: Steps towards EL2 support round 5, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 02/14] target-arm: lpae: Make t0sz and t1sz signed integers, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 01/14] target-arm: Add HPFAR_EL2, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 03/14] target-arm: lpae: Move declaration of t0sz and t1sz, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 05/14] target-arm: lpae: Replace tsz with computed inputsize, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 04/14] target-arm: Add support for AArch32 S2 negative t0sz,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH v5 06/14] target-arm: lpae: Rename granule_sz to stride, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 07/14] target-arm: Add computation of starting level for S2 PTW, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 08/14] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 09/14] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 10/14] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 11/14] target-arm: Add S2 translation to 64bit S1 PTWs, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 13/14] target-arm: Route S2 MMU faults to EL2, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 12/14] target-arm: Add S2 translation to 32bit S1 PTWs, Edgar E. Iglesias, 2015/10/26
- [Qemu-devel] [PATCH v5 14/14] target-arm: Add support for S1 + S2 MMU translations, Edgar E. Iglesias, 2015/10/26
- Re: [Qemu-devel] [PATCH v5 00/14] arm: Steps towards EL2 support round 5, Peter Maydell, 2015/10/27