Re: [Qemu-devel] [PATCH 3/3] target-xtensa: xtfpga: support noMMU cores

[Peter Maydell]

On 29 September 2015 at 11:34, Max Filippov <address@hidden> wrote:
> On Mon, Sep 28, 2015 at 12:59 AM, Peter Crosthwaite
> <address@hidden> wrote:
>> On Sun, Sep 27, 2015 at 2:48 PM, Max Filippov <address@hidden> wrote:
>>> On Mon, Sep 28, 2015 at 12:28 AM, Peter Crosthwaite
>>> <address@hidden> wrote:
>>>> To clarify, can you tell me the QEMU command line difference between
>>>> MMU and noMMU?
>>>
>>> There is no difference. You specify -cpu without full MMU -- you get
>>> noMMU address space layout.
>>
>> Ok but I think this is what we want to avoid. Using -cpu to switch up
>> the board/SoC architecture. The address space layout is SoC level (and
>> in your case a bitstream constitutes and entire SoC). There's a
>> lengthy discussion on this here:
>>
>> http://lists.gnu.org/archive/html/qemu-devel/2013-11/msg03979.html
>>
>> going back and forth from that point in the thread. Your hardware
>> model is more accurate that what was proposed by OP in that thread,
>> but it is good to keep the interfaces consistent with other machine
>> models.
>
> The message by the link says:
>
>   As Andreas says, we need to model real actual hardware,
>   not some abstraction that kind of matches the kernel's
>   abstractions.
>
> Changing address space layout according to CPU type is what happens
> in actual hardware. There are no user-controllable settings that would
> allow mismatching address space layout and CPU type on XTFPGA
> boards. There's also no SoC level mentioned in the developer guides
> for the corresponding boards. So I'm not sure what you're proposing to do.

I think this should clearly be different machine models
(possibly implemented using different SoC models). This isn't a
CPU-dependent thing at all, it's just your dev tools are hiding
"change the devices and other board/soc level things" behind a
CPU-type dropdown, which it can get away with because the whole
implementation is in a single FPGA.

Compare vexpress-a9 vs vexpress-a15 (which are modelling hardware
with a daughterboard with CPU and devices on it, which is sort
of analogous I think).

thanks
-- PMM