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[Qemu-devel] [PATCH RFC 1/8] target-arm: Add HPFAR_EL2
From: |
Edgar E. Iglesias |
Subject: |
[Qemu-devel] [PATCH RFC 1/8] target-arm: Add HPFAR_EL2 |
Date: |
Sat, 19 Sep 2015 07:15:20 -0700 |
From: "Edgar E. Iglesias" <address@hidden>
Signed-off-by: Edgar E. Iglesias <address@hidden>
---
target-arm/cpu.h | 1 +
target-arm/helper.c | 7 +++++++
2 files changed, 8 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 1b80516..e7694a5 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -280,6 +280,7 @@ typedef struct CPUARMState {
};
uint64_t far_el[4];
};
+ uint64_t hpfar_el2;
union { /* Translation result. */
struct {
uint64_t _unused_par_0;
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 12ea88f..b709582 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3221,6 +3221,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
{ .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
.access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
+ { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
+ .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
REGINFO_SENTINEL
};
@@ -3442,6 +3445,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.resetvalue = 0,
.writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
#endif
+ { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
+ .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
+ .access = PL2_RW,
+ .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
REGINFO_SENTINEL
};
--
1.9.1
- [Qemu-devel] [PATCH RFC 0/8] arm: Steps towards EL2 support round 5, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 1/8] target-arm: Add HPFAR_EL2,
Edgar E. Iglesias <=
- [Qemu-devel] [PATCH RFC 2/8] target-arm: Add computation of starting level for S2 PTW, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 3/8] target-arm: Add support for S2 page-table protection bits, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 4/8] target-arm: Avoid inline for get_phys_addr, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 5/8] target-arm: Add ARMMMUFaultInfo, Edgar E. Iglesias, 2015/09/19
- [Qemu-devel] [PATCH RFC 6/8] target-arm: Add S2 translation support for S1 PTW, Edgar E. Iglesias, 2015/09/19