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[Qemu-devel] [PULL 22/35] target-tilegx: Handle conditional branch instr
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 22/35] target-tilegx: Handle conditional branch instructions |
Date: |
Tue, 15 Sep 2015 08:04:00 -0700 |
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target-tilegx/translate.c | 51 +++++++++++++++++++++++++++++++++++------------
1 file changed, 38 insertions(+), 13 deletions(-)
diff --git a/target-tilegx/translate.c b/target-tilegx/translate.c
index c08a3a6..9c95633 100644
--- a/target-tilegx/translate.c
+++ b/target-tilegx/translate.c
@@ -1089,30 +1089,55 @@ static TileExcp gen_branch_opcode_x1(DisasContext *dc,
unsigned ext,
target_ulong tgt = dc->pc + off * TILEGX_BUNDLE_SIZE_IN_BYTES;
const char *mnemonic;
- switch (ext) {
- case BEQZT_BRANCH_OPCODE_X1:
+ dc->jmp.dest = tcg_const_tl(tgt);
+ dc->jmp.val1 = tcg_temp_new();
+ tcg_gen_mov_tl(dc->jmp.val1, load_gr(dc, srca));
+
+ /* Note that the "predict taken" opcodes have bit 0 clear.
+ Therefore, fold the two cases together by setting bit 0. */
+ switch (ext | 1) {
case BEQZ_BRANCH_OPCODE_X1:
- case BNEZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_EQ;
+ mnemonic = "beqz";
+ break;
case BNEZ_BRANCH_OPCODE_X1:
- case BLBC_BRANCH_OPCODE_X1:
- case BGEZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_NE;
+ mnemonic = "bnez";
+ break;
case BGEZ_BRANCH_OPCODE_X1:
- case BGTZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_GE;
+ mnemonic = "bgez";
+ break;
case BGTZ_BRANCH_OPCODE_X1:
- case BLBCT_BRANCH_OPCODE_X1:
- case BLBST_BRANCH_OPCODE_X1:
- case BLBS_BRANCH_OPCODE_X1:
- case BLEZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_GT;
+ mnemonic = "bgtz";
+ break;
case BLEZ_BRANCH_OPCODE_X1:
- case BLTZT_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_LE;
+ mnemonic = "blez";
+ break;
case BLTZ_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_LT;
+ mnemonic = "bltz";
+ break;
+ case BLBC_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_EQ;
+ tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
+ mnemonic = "blbc";
+ break;
+ case BLBS_BRANCH_OPCODE_X1:
+ dc->jmp.cond = TCG_COND_NE;
+ tcg_gen_andi_tl(dc->jmp.val1, dc->jmp.val1, 1);
+ mnemonic = "blbs";
+ break;
default:
return TILEGX_EXCP_OPCODE_UNIMPLEMENTED;
}
if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
- qemu_log("%s %s, " TARGET_FMT_lx " <%s>",
- mnemonic, reg_names[srca], tgt, lookup_symbol(tgt));
+ qemu_log("%s%s %s, " TARGET_FMT_lx " <%s>",
+ mnemonic, ext & 1 ? "" : "t",
+ reg_names[srca], tgt, lookup_symbol(tgt));
}
return TILEGX_EXCP_NONE;
}
--
2.4.3
- [Qemu-devel] [PULL 06/35] target-tilegx: Modify _SPECIAL_ opcodes, (continued)
- [Qemu-devel] [PULL 06/35] target-tilegx: Modify _SPECIAL_ opcodes, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 05/35] target-tilegx: Modify opcode_tilegx.h to fit QEMU usage, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 09/35] target-tilegx: Add cpu basic features for linux-user, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 12/35] target-tilegx: Generate SEGV properly, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 08/35] target-tilegx: Add special register information from Tilera Corporation, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 13/35] target-tilegx: Add TILE-Gx building files, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 10/35] target-tilegx: Add several helpers for instructions translation, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 17/35] target-arm: Use new revbit functions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 16/35] host-utils: Add revbit functions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 15/35] target-tilegx: Handle arithmetic instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 22/35] target-tilegx: Handle conditional branch instructions,
Richard Henderson <=
- [Qemu-devel] [PULL 18/35] target-tilegx: Handle most bit manipulation instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 20/35] target-tilegx: Handle post-increment load and store instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 11/35] target-tilegx: Framework for decoding bundles, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 23/35] target-tilegx: Handle comparison instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 19/35] target-tilegx: Handle basic load and store instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 14/35] target-tilegx: Handle simple logical operations, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 27/35] target-tilegx: Handle conditional move instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 25/35] target-tilegx: Handle bitfield instructions, Richard Henderson, 2015/09/15
- [Qemu-devel] [PULL 21/35] target-tilegx: Handle unconditional jump instructions, Richard Henderson, 2015/09/15