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Re: [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64
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From: |
Peter Maydell |
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Subject: |
Re: [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64 |
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Date: |
Fri, 11 Sep 2015 16:55:15 +0100 |
On 10 September 2015 at 19:18, Richard Henderson <address@hidden> wrote:
> Updated from v2 based on review from Peter.
>
> I did go ahead with the use of andc for translating ccmp; the result
> looked pretty good with Haswell's andn instruction.
>
>
> r~
Applied to target-arm.next, thanks.
-- PMM
- [Qemu-devel] [PATCH v3 02/11] target-arm: Introduce DisasCompare, (continued)
- [Qemu-devel] [PATCH v3 02/11] target-arm: Introduce DisasCompare, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 01/11] target-arm: Share all common TCG temporaries, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 04/11] target-arm: Use setcond and movcond for csel, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 07/11] target-arm: Recognize SXTB, SXTH, SXTW, ASR, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 08/11] target-arm: Recognize UXTB, UXTH, LSR, LSL, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 05/11] target-arm: Implement ccmp branchless, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 09/11] target-arm: Eliminate unnecessary zero-extend in disas_bitfield, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 11/11] target-arm: Use tcg_gen_extrh_i64_i32, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 06/11] target-arm: Implement fcsel with movcond, Richard Henderson, 2015/09/10
- [Qemu-devel] [PATCH v3 10/11] target-arm: Recognize ROR, Richard Henderson, 2015/09/10
- Re: [Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64,
Peter Maydell <=