[Qemu-devel] [PATCH v3 00/11] target-arm improvments for aarch64

[Richard Henderson]

Updated from v2 based on review from Peter.

I did go ahead with the use of andc for translating ccmp; the result
looked pretty good with Haswell's andn instruction.


r~


Richard Henderson (11):
  target-arm: Share all common TCG temporaries
  target-arm: Introduce DisasCompare
  target-arm: Handle always condition codes within arm_test_cc
  target-arm: Use setcond and movcond for csel
  target-arm: Implement ccmp branchless
  target-arm: Implement fcsel with movcond
  target-arm: Recognize SXTB, SXTH, SXTW, ASR
  target-arm: Recognize UXTB, UXTH, LSR, LSL
  target-arm: Eliminate unnecessary zero-extend in disas_bitfield
  target-arm: Recognize ROR
  target-arm: Use tcg_gen_extrh_i64_i32

 target-arm/translate-a64.c | 340 ++++++++++++++++++++++++++-------------------
 target-arm/translate.c     | 134 +++++++++++-------
 target-arm/translate.h     |  17 +++
 3 files changed, 299 insertions(+), 192 deletions(-)

-- 
2.4.3