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[Qemu-devel] [PULL 11/20] hw/arm/virt: Enable TZ extensions on the GIC i
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/20] hw/arm/virt: Enable TZ extensions on the GIC if we are using them |
Date: |
Tue, 8 Sep 2015 17:51:23 +0100 |
If we're creating a board with support for TrustZone, then enable
it on the GIC model as well as on the CPUs.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Peter Crosthwaite <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
---
hw/arm/virt.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a067748..e9324f5 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -396,7 +396,7 @@ static void create_v2m(VirtBoardInfo *vbi, qemu_irq *pic)
fdt_add_v2m_gic_node(vbi);
}
-static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
+static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic, bool secure)
{
/* We create a standalone GIC v2 */
DeviceState *gicdev;
@@ -413,6 +413,9 @@ static void create_gic(VirtBoardInfo *vbi, qemu_irq *pic)
* interrupts; there are always 32 of the former (mandated by GIC spec).
*/
qdev_prop_set_uint32(gicdev, "num-irq", NUM_IRQS + 32);
+ if (!kvm_irqchip_in_kernel()) {
+ qdev_prop_set_bit(gicdev, "has-security-extensions", secure);
+ }
qdev_init_nofail(gicdev);
gicbusdev = SYS_BUS_DEVICE(gicdev);
sysbus_mmio_map(gicbusdev, 0, vbi->memmap[VIRT_GIC_DIST].base);
@@ -967,7 +970,7 @@ static void machvirt_init(MachineState *machine)
create_flash(vbi);
- create_gic(vbi, pic);
+ create_gic(vbi, pic, vms->secure);
create_uart(vbi, pic);
--
1.9.1
- [Qemu-devel] [PULL 00/20] target-arm queue, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 19/20] xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 20/20] xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 18/20] ahci.c: Don't assume AHCIState's parent is AHCIPCIState, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 16/20] cadence_gem: Correct Marvell PHY SPCFC reset value, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 15/20] target-arm: Add AArch64 access to PAR_EL1, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 14/20] target-arm: Correct opc1 for AT_S12Exx, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 13/20] target-arm: Log the target EL when taking exceptions, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 11/20] hw/arm/virt: Enable TZ extensions on the GIC if we are using them,
Peter Maydell <=
- [Qemu-devel] [PULL 06/20] qom: Add recursive version of object_child_for_each, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 05/20] hw/intc/arm_gic: Actually set the active bits for active interrupts, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 01/20] armv7m_nvic: Implement ICSR without using internal GIC state, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 08/20] hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 04/20] hw/intc/arm_gic: Drop running_irq and last_active arrays, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 12/20] target-arm: Fix default_exception_el() function for the case when EL3 is not supported, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 07/20] hw/arm: new interface for devices which need to behave differently for kernel boot, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 17/20] ahci: Separate the AHCI state structure into the header, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 10/20] hw/arm/virt: Default to not providing TrustZone support, Peter Maydell, 2015/09/08
- [Qemu-devel] [PULL 09/20] hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs, Peter Maydell, 2015/09/08