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[Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call |
Date: |
Fri, 4 Sep 2015 16:05:37 +0100 |
The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Christopher Covington <address@hidden>
Tested-by: Christopher Covington <address@hidden>
Message-id: address@hidden
---
target-arm/arm-semi.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/target-arm/arm-semi.c b/target-arm/arm-semi.c
index 1d4cc59..1d0d7aa 100644
--- a/target-arm/arm-semi.c
+++ b/target-arm/arm-semi.c
@@ -58,6 +58,7 @@
#define TARGET_SYS_GET_CMDLINE 0x15
#define TARGET_SYS_HEAPINFO 0x16
#define TARGET_SYS_EXIT 0x18
+#define TARGET_SYS_SYNCCACHE 0x19
/* ADP_Stopped_ApplicationExit is used for exit(0),
* anything else is implemented as exit(1) */
@@ -623,6 +624,15 @@ target_ulong do_arm_semihosting(CPUARMState *env)
ret = (args == ADP_Stopped_ApplicationExit) ? 0 : 1;
gdb_exit(env, ret);
exit(ret);
+ case TARGET_SYS_SYNCCACHE:
+ /* Clean the D-cache and invalidate the I-cache for the specified
+ * virtual address range. This is a nop for us since we don't
+ * implement caches. This is only present on A64.
+ */
+ if (is_a64(env)) {
+ return 0;
+ }
+ /* fall through -- invalid for A32/T32 */
default:
fprintf(stderr, "qemu: Unsupported SemiHosting SWI 0x%02x\n", nr);
cpu_dump_state(cs, stderr, fprintf, 0);
--
1.9.1
- [Qemu-devel] [PULL 05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]', (continued)
- [Qemu-devel] [PULL 05/27] target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]', Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 22/27] i.MX: Add SOC support for i.MX25, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 14/27] arm: Remove hw_error() usages., Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 19/27] i.MX: KZM: use standalone i.MX31 SOC support, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 15/27] target-arm: Fix AArch32:AArch64 general-purpose register mapping, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 17/27] target-arm: Fix arm_excp_unmasked() function, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 10/27] target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 25/27] i.MX: Add i2C devices to i.MX31 SOC, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 23/27] i.MX: Add the i.MX25 PDK platform, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 11/27] smbios: add smbios 3.0 support, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 08/27] target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call,
Peter Maydell <=
- [Qemu-devel] [PULL 13/27] arm: cpu: assert() on no-EL2 virt IRQ error condition., Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 09/27] target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 16/27] hw/arm/virt: Add high MMIO PCI region, 512G in size, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 21/27] i.MX: Add FEC Ethernet Emulator, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 18/27] i.MX: Add SOC support for i.MX31, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 20/27] i.MX: Add I2C controller emulator, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 02/27] target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 12/27] smbios: implement smbios support for mach-virt, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 03/27] target-arm: Improve semihosting debug prints, Peter Maydell, 2015/09/04
- [Qemu-devel] [PULL 27/27] arm/virt: Add full-sized CPU affinity handling, Peter Maydell, 2015/09/04