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[Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operation
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations |
Date: |
Tue, 25 Aug 2015 16:00:08 +0100 |
Implement the AArch32 ATS1H* operations which perform
Hyp mode stage 1 translations.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
---
target-arm/helper.c | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 4b2fc090..6c55cc4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -1849,6 +1849,17 @@ static void ats_write(CPUARMState *env, const
ARMCPRegInfo *ri, uint64_t value)
A32_BANKED_CURRENT_REG_SET(env, par, par64);
}
+static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri,
+ uint64_t value)
+{
+ int access_type = ri->opc2 & 1;
+ uint64_t par64;
+
+ par64 = do_ats_write(env, value, access_type, ARMMMUIdx_S2NS);
+
+ A32_BANKED_CURRENT_REG_SET(env, par, par64);
+}
+
static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo *ri)
{
if (arm_current_el(env) == 3 && !(env->cp15.scr_el3 & SCR_NS)) {
@@ -3066,6 +3077,17 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
.opc0 = 1, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
.access = PL2_W, .accessfn = at_s1e2_access,
.type = ARM_CP_NO_RAW, .writefn = ats_write64 },
+ /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE
+ * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3
+ * with SCR.NS == 0 outside Monitor mode is UNPREDICTABLE; we choose
+ * to behave as if SCR.NS was 1.
+ */
+ { .name = "ATS1HR", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 0,
+ .access = PL2_W,
+ .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
+ { .name = "ATS1HW", .cp = 15, .opc1 = 4, .crn = 7, .crm = 8, .opc2 = 1,
+ .access = PL2_W,
+ .writefn = ats1h_write, .type = ARM_CP_NO_RAW },
{ .name = "CNTHCTL_EL2", .state = ARM_CP_STATE_BOTH,
.opc0 = 3, .opc1 = 4, .crn = 14, .crm = 1, .opc2 = 0,
/* ARMv7 requires bit 0 and 1 to reset to 1. ARMv8 defines the
--
1.9.1
- [Qemu-devel] [PULL 18/20] target-arm: Implement missing EL2 TLBI operations, (continued)
- [Qemu-devel] [PULL 18/20] target-arm: Implement missing EL2 TLBI operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 19/20] target-arm: Implement missing EL3 TLB invalidate operations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 10/20] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 07/20] target-arm: Implement missing ACTLR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 09/20] target-arm: Wire up AArch64 EL2 and EL3 address translation ops, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 06/20] target-arm: Implement missing AFSR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 20/20] target-arm: Implement AArch64 TLBI operations on IPAs, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 05/20] target-arm: Implement missing AMAIR registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 04/20] target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 11/20] target-arm: Enable the AArch32 ATS12NSO ops, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 12/20] target-arm: Implement AArch32 ATS1H* operations,
Peter Maydell <=
- [Qemu-devel] [PULL 01/20] xlnx-zynqmp: Connect the four OCM banks, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 17/20] target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 03/20] MAINTAINERS: Add ZynqMP to MAINTAINERS file, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 16/20] target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 13/20] smbios: add smbios 3.0 support, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 14/20] smbios: implement smbios support for mach-virt, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 08/20] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 02/20] MAINTAINERS: Update Xilinx Maintainership, Peter Maydell, 2015/08/25
- [Qemu-devel] [PULL 15/20] cputlb: Add functions for flushing TLB for a single MMU index, Peter Maydell, 2015/08/25