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Re: [Qemu-devel] [PATCH 2/4] target-arm: Implement missing AMAIR registe


From: Edgar E. Iglesias
Subject: Re: [Qemu-devel] [PATCH 2/4] target-arm: Implement missing AMAIR registers
Date: Mon, 17 Aug 2015 00:02:42 +0200
User-agent: Mutt/1.5.21 (2010-09-15)

On Thu, Jul 30, 2015 at 07:36:36PM +0100, Peter Maydell wrote:
> The AMAIR registers are for providing auxiliary implementation
> defined memory attributes. We already implemented a RAZ/WI
> AMAIR_EL1; add the EL2 and EL3 versions for consistency.
> 
> Signed-off-by: Peter Maydell <address@hidden>

Reviewed-by: Edgar E. Iglesias <address@hidden>


> ---
>  target-arm/helper.c | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
> 
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index d59616e..781b3a2 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -2602,6 +2602,14 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
>      { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
>        .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> +    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
> +      .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> @@ -2696,6 +2704,15 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
>        .opc1 = 4, .crn = 10, .crm = 2, .opc2 = 1,
>        .access = PL2_RW, .type = ARM_CP_ALIAS,
>        .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el[2]) },
> +    { .name = "AMAIR_EL2", .state = ARM_CP_STATE_BOTH,
> +      .opc0 = 3, .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 0,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
> +    /* HAMAIR1 is mapped to AMAIR_EL2[63:32] */
> +    { .name = "HMAIR1", .state = ARM_CP_STATE_AA32,
> +      .opc1 = 4, .crn = 10, .crm = 3, .opc2 = 1,
> +      .access = PL2_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH,
>        .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2,
>        .access = PL2_RW, .writefn = vmsa_tcr_el1_write,
> @@ -2798,6 +2815,10 @@ static const ARMCPRegInfo el3_cp_reginfo[] = {
>        .opc0 = 3, .opc1 = 6, .crn = 13, .crm = 0, .opc2 = 2,
>        .access = PL3_RW, .resetvalue = 0,
>        .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[3]) },
> +    { .name = "AMAIR_EL3", .state = ARM_CP_STATE_AA64,
> +      .opc0 = 3, .opc1 = 6, .crn = 10, .crm = 3, .opc2 = 0,
> +      .access = PL3_RW, .type = ARM_CP_CONST,
> +      .resetvalue = 0 },
>      REGINFO_SENTINEL
>  };
>  
> -- 
> 1.9.1
> 



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