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[Qemu-devel] [mttcg RFC v4 6/6] target-arm: Use a runtime helper for exc
From: |
Alvise Rigo |
Subject: |
[Qemu-devel] [mttcg RFC v4 6/6] target-arm: Use a runtime helper for excl accesses |
Date: |
Fri, 14 Aug 2015 17:55:32 +0200 |
Instead of using TCG's load and store instructions, use a runtime helper
as a hook for the slow-path.
This is a proof of concept to verify that this approach is actually
working.
At the moment only the 32bit STREX is relying on this new code-path and
it's working as expected.
Signed-off-by: Alvise Rigo <address@hidden>
---
target-arm/helper.h | 2 ++
target-arm/op_helper.c | 11 +++++++++++
target-arm/translate.c | 12 +++++++++++-
3 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/target-arm/helper.h b/target-arm/helper.h
index c77bf04..c4da74a 100644
--- a/target-arm/helper.h
+++ b/target-arm/helper.h
@@ -534,6 +534,8 @@ DEF_HELPER_4(atomic_cmpxchg64, i32, env, i32, i64, i32)
DEF_HELPER_1(atomic_clear, void, env)
DEF_HELPER_3(atomic_claim, void, env, i32, i64)
+DEF_HELPER_4(stcond_aa32_i32, i32, env, i32, i32, i32)
+
#ifdef TARGET_AARCH64
#include "helper-a64.h"
#endif
diff --git a/target-arm/op_helper.c b/target-arm/op_helper.c
index ba8c5f5..53dcdde 100644
--- a/target-arm/op_helper.c
+++ b/target-arm/op_helper.c
@@ -1095,3 +1095,14 @@ uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x,
uint32_t i)
return ((uint32_t)x >> shift) | (x << (32 - shift));
}
}
+
+uint32_t HELPER(stcond_aa32_i32)(CPUARMState *env, uint32_t val, uint32_t addr,
+ uint32_t index)
+{
+ CPUArchState *state = env;
+ TCGMemOpIdx op;
+
+ op = make_memop_idx(MO_LEUL, index);
+
+ return helper_le_stcondl_mmu(state, addr, val, op, 0);
+}
diff --git a/target-arm/translate.c b/target-arm/translate.c
index d90a27b..591ce97 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1006,6 +1006,17 @@ static inline void gen_aa32_stex64(TCGv_i32 is_dirty,
TCGv_i64 val,
#endif
+/* Use the runtime helper for 32bit exclusive stores. */
+static inline void gen_aa32_stex32(TCGv_i32 is_dirty, TCGv_i32 val,
+ TCGv_i32 addr, int index)
+{
+ TCGv index_tmp = tcg_temp_new_i32();
+
+ tcg_gen_movi_i32(index_tmp, index);
+ gen_helper_stcond_aa32_i32(is_dirty, cpu_env, val, addr, index_tmp);
+ tcg_temp_free_i32(index_tmp);
+}
+
DO_GEN_LD(8s, MO_SB)
DO_GEN_LD(8u, MO_UB)
DO_GEN_LD(8uex, MO_UB | MO_EXCL)
@@ -1021,7 +1032,6 @@ DO_GEN_ST(32, MO_TEUL)
/* Load/Store exclusive generators (always unsigned) */
DO_GEN_STEX(8, MO_UB)
DO_GEN_STEX(16, MO_TEUW)
-DO_GEN_STEX(32, MO_TEUL)
static inline void gen_set_pc_im(DisasContext *s, target_ulong val)
{
--
2.5.0
- [Qemu-devel] [mttcg RFC v4 0/6] Atomic slow-path for mttcg, Alvise Rigo, 2015/08/14
- [Qemu-devel] [mttcg RFC v4 4/6] softmmu_llsc_template.h: move to multithreading, Alvise Rigo, 2015/08/14
- [Qemu-devel] [mttcg RFC v4 1/6] cpus: async_run_on_cpu: kick only if needed, Alvise Rigo, 2015/08/14
- [Qemu-devel] [mttcg RFC v4 2/6] cputlb: wrap tlb_flush with the a new function, Alvise Rigo, 2015/08/14
- [Qemu-devel] [mttcg RFC v4 3/6] exec: ram_addr: Fix exclusive bitmap accessor, Alvise Rigo, 2015/08/14
- [Qemu-devel] [mttcg RFC v4 6/6] target-arm: Use a runtime helper for excl accesses,
Alvise Rigo <=
- [Qemu-devel] [mttcg RFC v4 5/6] softmmu_template.h: move to multithreading, Alvise Rigo, 2015/08/14