Re: [Qemu-devel] [PATCH v2 2/2] fw_cfg: document MMIO registers for arm, sun4*, and ppc/mac_*

[Laszlo Ersek]

On 08/06/15 01:47, Gabriel L. Somlo wrote:
> Signed-off-by: Gabriel Somlo <address@hidden>
> ---
>  docs/specs/fw_cfg.txt | 22 +++++++++++++++++++---
>  1 file changed, 19 insertions(+), 3 deletions(-)
> 
> diff --git a/docs/specs/fw_cfg.txt b/docs/specs/fw_cfg.txt
> index 5bc7b96..f37e1ad 100644
> --- a/docs/specs/fw_cfg.txt
> +++ b/docs/specs/fw_cfg.txt
> @@ -72,10 +72,26 @@ increasing address order, similar to memcpy().
>  
>  == Register Locations ==
>  
> -=== x86, x86_64 Register Locations ===
> +=== x86, x86_64, sun4u Register Locations ===
> +
> +Selector Register IOport: 0x510 (16-bit, little-endian)
> +Data Register IOport:     0x511 (8-bit)
> +
> +=== arm Register Locations ===
> +
> +Selector Register MMIO addr: 0x9020008 (16-bit, big-endian)
> +Data Register MMIO addr:     0x9020000 (64-bit)

Suggestions:
- maybe mention that this is specific to the "virt" machtype
- mention that the exact location comes from the DTB,
  and hint at "Documentation/devicetree/bindings/arm/fw-cfg.txt" in the
  kernel tree
- for the data register, rather than just "(64-bit)", consider saying
  "(64-bit, endianless, string-preserving)"

> +
> +=== sun4m Register Locations ===
> +
> +Selector Register MMIO addr: 0xd00000510 (16-bit, big-endian)
> +Data Register MMIO addr:     0xd00000512 (8-bit)
> +
> +=== ppc/mac Register Locations ===
> +
> +Selector Register MMIO addr: 0xf0000510 (16-bit, big-endian)
> +Data Register MMIO addr:     0xf0000512 (8-bit)

Should these be tied to machine types? (I got no clue, I've never even
built these targets.)

Thanks
Laszlo

>  
> -Selector Register IOport: 0x510
> -Data Register IOport:     0x511
>  
>  == Firmware Configuration Items ==
>  
>