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[Qemu-devel] [PATCH 1/5] target-arm: there is no TTBR1 for 32-bit EL2 st
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PATCH 1/5] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations |
Date: |
Fri, 24 Jul 2015 16:20:59 +0100 |
For EL2 stage 1 translations, there is no TTBR1. We were already
handling this for 64-bit EL2; add the code to take the 'no TTBR1'
code path for 64-bit EL2 as well.
Signed-off-by: Peter Maydell <address@hidden>
---
target-arm/helper.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 01f0d0d..1ac6594 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -5638,6 +5638,11 @@ static bool get_phys_addr_lpae(CPUARMState *env,
target_ulong address,
if (el > 1) {
ttbr1_valid = false;
}
+ } else {
+ /* There is no TTBR1 for EL2 */
+ if (el == 2) {
+ ttbr1_valid = false;
+ }
}
/* Determine whether this address is in the region controlled by
--
1.9.1
- [Qemu-devel] [PATCH 0/5] Wire up various EL2/EL3 address translation ops, Peter Maydell, 2015/07/24
- [Qemu-devel] [PATCH 2/5] target-arm: Wire up AArch64 EL2 and EL3 address translation ops, Peter Maydell, 2015/07/24
- [Qemu-devel] [PATCH 3/5] target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3, Peter Maydell, 2015/07/24
- [Qemu-devel] [PATCH 4/5] target-arm: Enable the AArch32 ATS12NSO ops, Peter Maydell, 2015/07/24
- [Qemu-devel] [PATCH 5/5] target-arm: Implement AArch32 ATS1H* operations, Peter Maydell, 2015/07/24
- [Qemu-devel] [PATCH 1/5] target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations,
Peter Maydell <=