[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v6 01/10] softmmu: add helper function to pass t
From: |
Aurelien Jarno |
Subject: |
Re: [Qemu-devel] [PATCH v6 01/10] softmmu: add helper function to pass through retaddr |
Date: |
Thu, 9 Jul 2015 17:28:26 +0200 |
User-agent: |
Mutt/1.5.23 (2014-03-12) |
On 2015-07-07 16:31, Pavel Dovgalyuk wrote:
> This patch introduces several helpers to pass return address
> which points to the TB. Correct return address allows correct
> restoring of the guest PC and icount. These functions should be used when
> helpers embedded into TB invoke memory operations.
>
> Reviewed-by: Aurelien Jarno <address@hidden>
>
> Signed-off-by: Pavel Dovgalyuk <address@hidden>
> ---
> include/exec/cpu_ldst_template.h | 59
> +++++++++++++++++++++++++----
> include/exec/cpu_ldst_useronly_template.h | 25 ++++++++++++
> softmmu_template.h | 6 ---
> tcg/tcg.h | 23 +++++++++++
> 4 files changed, 99 insertions(+), 14 deletions(-)
>
With this patch some functions becomes unused. Given the softmmu code is
already quite complex, it might be a good idea to remove them. Here is a
patch to do that, you can add it to the series, or squash it into this
one.
From: Aurelien Jarno <address@hidden>
softmmu: remove now unused functions
Now that the cpu_ld/st_* function directly call helper_ret_ld/st, we can
drop the old helper_ld/st functions.
Signed-off-by: Aurelien Jarno <address@hidden>
---
include/exec/cpu_ldst.h | 19 -------------------
softmmu_template.h | 16 ----------------
2 files changed, 35 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index 1239c60..91c8ffb 100644
--- a/include/exec/cpu_ldst.h
+++ b/include/exec/cpu_ldst.h
@@ -113,25 +113,6 @@
/* The memory helpers for tcg-generated code need tcg_target_long etc. */
#include "tcg.h"
-uint8_t helper_ldb_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint16_t helper_ldw_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint32_t helper_ldl_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-
-void helper_stb_mmu(CPUArchState *env, target_ulong addr,
- uint8_t val, int mmu_idx);
-void helper_stw_mmu(CPUArchState *env, target_ulong addr,
- uint16_t val, int mmu_idx);
-void helper_stl_mmu(CPUArchState *env, target_ulong addr,
- uint32_t val, int mmu_idx);
-void helper_stq_mmu(CPUArchState *env, target_ulong addr,
- uint64_t val, int mmu_idx);
-
-uint8_t helper_ldb_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint16_t helper_ldw_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint32_t helper_ldl_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-uint64_t helper_ldq_cmmu(CPUArchState *env, target_ulong addr, int mmu_idx);
-
#ifdef MMU_MODE0_SUFFIX
#define CPU_MMU_INDEX 0
#define MEMSUFFIX MMU_MODE0_SUFFIX
diff --git a/softmmu_template.h b/softmmu_template.h
index a4c1016..fb216c3 100644
--- a/softmmu_template.h
+++ b/softmmu_template.h
@@ -329,14 +329,6 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env,
target_ulong addr,
}
#endif /* DATA_SIZE > 1 */
-DATA_TYPE
-glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
- int mmu_idx)
-{
- TCGMemOpIdx oi = make_memop_idx(SHIFT, mmu_idx);
- return helper_te_ld_name (env, addr, oi, GETRA());
-}
-
#ifndef SOFTMMU_CODE_ACCESS
/* Provide signed versions of the load routines as well. We can of course
@@ -534,14 +526,6 @@ void helper_be_st_name(CPUArchState *env, target_ulong
addr, DATA_TYPE val,
}
#endif /* DATA_SIZE > 1 */
-void
-glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr,
- DATA_TYPE val, int mmu_idx)
-{
- TCGMemOpIdx oi = make_memop_idx(SHIFT, mmu_idx);
- helper_te_st_name(env, addr, val, oi, GETRA());
-}
-
#if DATA_SIZE == 1
/* Probe for whether the specified guest write access is permitted.
* If it is not permitted then an exception will be taken in the same
--
2.1.4
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
address@hidden http://www.aurel32.net
- [Qemu-devel] [PATCH v6 00/10] Fix exceptions handling for MIPS, PowerPC, and i386, Pavel Dovgalyuk, 2015/07/07
- [Qemu-devel] [PATCH v6 10/10] target-ppc: exceptions handling in icount mode, Pavel Dovgalyuk, 2015/07/07
- [Qemu-devel] [PATCH v6 06/10] target-i386: exception handling for div instructions, Pavel Dovgalyuk, 2015/07/07
- [Qemu-devel] [PATCH v6 05/10] target-i386: exception handling for FPU instructions, Pavel Dovgalyuk, 2015/07/07