Re: [Qemu-devel] QEMU ARM SMP: IPI delivery delayed until next main loop event // how to improve IPI latency?

[Peter Maydell]

On 15 June 2015 at 16:05, Alex Züpke <address@hidden> wrote:
> Here's a simple IPI tester sending IPIs from CPU #0 to CPU #1 in an endless 
> loop.
> The IPIs are delayed until the timer interrupt triggers the main loop.
>
> http://www.cs.hs-rm.de/~zuepke/qemu/ipi.elf
> 3174 bytes, md5sum 8d73890a60cd9b24a4f9139509b580e2
>
> Run testcase:
> $ qemu-system-arm -M vexpress-a15 -smp 2 -kernel ipi.elf -nographic
>
> The testcase prints the following on the serial console without the patch:
>
>   +------- CPU 0 came up
>   |+------ CPU 0 initialization completed
>   || +---- CPU 0 timer interrupt, 1 HZ
>   || |
>   vv v
>   0!1T.T.T.T.T.T.T.
>     ^ ^
>     | |
>     | +-- CPU 1 received an IPI
>     +---- CPU 1 came up
>
>
> Expected testcase output with patch:
>
>   0!1T..............<hundreds of dots>.................T...............
>
> So: more dots == more IPIs handled between two timer interrupts "T" ...

For me this test case (without any IPI related patches)
just prints "0!TT" (or sometimes "0!T") and then hangs.
The yield test binary does the same thing.

-- PMM