[Qemu-devel] [PATCH v3 3/8] target-sh4: optimize addc using add2

[Aurelien Jarno]

Signed-off-by: Aurelien Jarno <address@hidden>
---
 target-sh4/translate.c | 14 ++++++--------
 1 file changed, 6 insertions(+), 8 deletions(-)

diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index f9bc24c..a7a8f39 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -642,17 +642,15 @@ static void _decode_opc(DisasContext * ctx)
        return;
     case 0x300e:               /* addc Rm,Rn */
         {
-            TCGv t0, t1;
-            t0 = tcg_temp_new();
+            TCGv t0, t1, t2;
+            t0 = tcg_const_tl(0);
             t1 = tcg_temp_new();
-            tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8));
-            tcg_gen_add_i32(t1, cpu_sr_t, t0);
-            tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), t0);
-            tcg_gen_setcond_i32(TCG_COND_GTU, t0, t0, t1);
-            tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, t0);
+            t2 = tcg_temp_new();
+            tcg_gen_add2_i32(t1, t2, REG(B11_8), t0, REG(B7_4), t0);
+            tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, t1, t2, cpu_sr_t, t0);
             tcg_temp_free(t0);
-            tcg_gen_mov_i32(REG(B11_8), t1);
             tcg_temp_free(t1);
+            tcg_temp_free(t2);
         }
        return;
     case 0x300f:               /* addv Rm,Rn */
-- 
2.1.4