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Re: [Qemu-devel] [PATCH v2 5/9] target-arm: Extend FP checks to use an E
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v2 5/9] target-arm: Extend FP checks to use an EL |
Date: |
Mon, 18 May 2015 18:40:08 +0100 |
On 22 April 2015 at 18:09, Greg Bellows <address@hidden> wrote:
> Extend the ARM disassemble context to take a target exception EL instead of a
> boolean enable. This change reverses the polarity of the check making a value
> of 0 indicate floating point enabled (no exception).
>
> Signed-off-by: Greg Bellows <address@hidden>
> ---
> target-arm/cpu.h | 63
> +++++++++++++++++++++++++++++++++++-----------
> target-arm/translate-a64.c | 8 +++---
> target-arm/translate.c | 17 ++++++-------
> target-arm/translate.h | 2 +-
> 4 files changed, 61 insertions(+), 29 deletions(-)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index d61bb3f..c7808da 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -1773,11 +1773,14 @@ static inline bool arm_singlestep_active(CPUARMState
> *env)
> #define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
>
> /* Bit usage when in AArch64 state */
> +/* The floating-point mask in AArch64 is 2 bits to carry the target exception
> + * EL is not enabled.
> + */
> #define ARM_TBFLAG_AA64_FPEN_SHIFT 2
> -#define ARM_TBFLAG_AA64_FPEN_MASK (1 << ARM_TBFLAG_AA64_FPEN_SHIFT)
> -#define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 3
> +#define ARM_TBFLAG_AA64_FPEN_MASK (0x3 << ARM_TBFLAG_AA64_FPEN_SHIFT)
> +#define ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT 4
> #define ARM_TBFLAG_AA64_SS_ACTIVE_MASK (1 << ARM_TBFLAG_AA64_SS_ACTIVE_SHIFT)
> -#define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 4
> +#define ARM_TBFLAG_AA64_PSTATE_SS_SHIFT 5
> #define ARM_TBFLAG_AA64_PSTATE_SS_MASK (1 << ARM_TBFLAG_AA64_PSTATE_SS_SHIFT)
>
> /* some convenience accessor macros */
> @@ -1814,24 +1817,55 @@ static inline bool arm_singlestep_active(CPUARMState
> *env)
> #define ARM_TBFLAG_NS(F) \
> (((F) & ARM_TBFLAG_NS_MASK) >> ARM_TBFLAG_NS_SHIFT)
>
> -static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
> - target_ulong *cs_base, int *flags)
> +/* Function to determine if floating point is disabled and what EL FP
> + * operations should be trapped to. If FP is enabled 0 is returned.
> + */
> +static inline int get_fp_exception_el(CPUARMState *env)
> {
> int fpen;
> + int cur_el = arm_current_el(env);
>
> + /* CPACR doesn't exist before v6, so VFP is always accessible */
> if (arm_feature(env, ARM_FEATURE_V6)) {
> fpen = extract32(env->cp15.c1_coproc, 20, 2);
this would be easier to read as
if (!v6) {
return 0;
}
rather than putting the bulk of the function in an else clause.
> - } else {
> - /* CPACR doesn't exist before v6, so VFP is always accessible */
> - fpen = 3;
> +
> + /* If we are less than EL2, check if the CPACR has floating point
> + * enabled. If not, return a trap to EL1.
> + */
> + if ((cur_el == 0 && fpen == 1) ||
> + (cur_el < 2 && (fpen == 0 || fpen == 2))) {
> + return 1;
> + }
> +
> + /* The CPTR registers only exist in ARMv8 */
> + if (arm_feature(env, ARM_FEATURE_V8)) {
> + /* Check whether floating point operations are trapped to EL2 */
> + if (cur_el < 2 && extract32(env->cp15.cptr_el[2], 10, 1)) {
> + return 2;
> + }
> +
> + /* Check whether floating point operations are trapped to EL3 */
> + if (cur_el < 3 && extract32(env->cp15.cptr_el[3], 10, 1)) {
> + return 3;
> + }
> + }
> }
>
> + return 0;
> +}
> +
> +static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
> + target_ulong *cs_base, int *flags)
> +{
> + int fp_excp_el = get_fp_exception_el(env);
> +
> if (is_a64(env)) {
> *pc = env->pc;
> *flags = ARM_TBFLAG_AARCH64_STATE_MASK;
> - if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) {
> - *flags |= ARM_TBFLAG_AA64_FPEN_MASK;
> - }
> +
> + /* Add the target FP exception EL to the flags */
> + *flags |= fp_excp_el << ARM_TBFLAG_AA64_FPEN_SHIFT;
> +
> /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
> * states defined in the ARM ARM for software singlestep:
> * SS_ACTIVE PSTATE.SS State
> @@ -1859,9 +1893,10 @@ static inline void cpu_get_tb_cpu_state(CPUARMState
> *env, target_ulong *pc,
> || arm_el_is_aa64(env, 1)) {
> *flags |= ARM_TBFLAG_VFPEN_MASK;
> }
> - if (fpen == 3 || (fpen == 1 && arm_current_el(env) != 0)) {
> - *flags |= ARM_TBFLAG_CPACR_FPEN_MASK;
> - }
> +
> + /* Add the target FP exception EL to the flags */
> + *flags |= fp_excp_el << ARM_TBFLAG_CPACR_FPEN_SHIFT;
You didn't make this tb flags field 2 bits wide...
(We should probably bite the bullet and tidy up the flags fields a bit
so more of the common flags are really common.)
> +
> /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine
> * states defined in the ARM ARM for software singlestep:
> * SS_ACTIVE PSTATE.SS State
> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
> index b1f44c9..b4423ca 100644
> --- a/target-arm/translate-a64.c
> +++ b/target-arm/translate-a64.c
> @@ -412,7 +412,7 @@ static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg,
> int sf)
> static inline void assert_fp_access_checked(DisasContext *s)
> {
> #ifdef CONFIG_DEBUG_TCG
> - if (unlikely(!s->fp_access_checked || !s->cpacr_fpen)) {
> + if (unlikely(!s->fp_access_checked || s->fp_excp_el)) {
> fprintf(stderr, "target-arm: FP access check missing for "
> "instruction 0x%08x\n", s->insn);
> abort();
> @@ -972,12 +972,12 @@ static inline bool fp_access_check(DisasContext *s)
> assert(!s->fp_access_checked);
> s->fp_access_checked = true;
>
> - if (s->cpacr_fpen) {
> + if (!s->fp_excp_el) {
> return true;
> }
>
> gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false),
> - default_exception_el(s));
> + s->fp_excp_el);
> return false;
> }
>
> @@ -10954,7 +10954,7 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu,
> #if !defined(CONFIG_USER_ONLY)
> dc->user = (dc->current_el == 0);
> #endif
> - dc->cpacr_fpen = ARM_TBFLAG_AA64_FPEN(tb->flags);
> + dc->fp_excp_el = ARM_TBFLAG_AA64_FPEN(tb->flags);
> dc->vec_len = 0;
> dc->vec_stride = 0;
> dc->cp_regs = cpu->cp_regs;
> diff --git a/target-arm/translate.c b/target-arm/translate.c
> index 2bd5733..0d9b856 100644
> --- a/target-arm/translate.c
> +++ b/target-arm/translate.c
> @@ -3044,10 +3044,9 @@ static int disas_vfp_insn(DisasContext *s, uint32_t
> insn)
> * for invalid encodings; we will generate incorrect syndrome information
> * for attempts to execute invalid vfp/neon encodings with FP disabled.
> */
> - if (!s->cpacr_fpen) {
> + if (s->fp_excp_el) {
> gen_exception_insn(s, 4, EXCP_UDEF,
> - syn_fp_access_trap(1, 0xe, s->thumb),
> - default_exception_el(s));
> + syn_fp_access_trap(1, 0xe, s->thumb),
> s->fp_excp_el);
> return 0;
> }
>
> @@ -4363,10 +4362,9 @@ static int disas_neon_ls_insn(DisasContext *s,
> uint32_t insn)
> * for invalid encodings; we will generate incorrect syndrome information
> * for attempts to execute invalid vfp/neon encodings with FP disabled.
> */
> - if (!s->cpacr_fpen) {
> + if (s->fp_excp_el) {
> gen_exception_insn(s, 4, EXCP_UDEF,
> - syn_fp_access_trap(1, 0xe, s->thumb),
> - default_exception_el(s));
> + syn_fp_access_trap(1, 0xe, s->thumb),
> s->fp_excp_el);
> return 0;
> }
>
> @@ -5102,10 +5100,9 @@ static int disas_neon_data_insn(DisasContext *s,
> uint32_t insn)
> * for invalid encodings; we will generate incorrect syndrome information
> * for attempts to execute invalid vfp/neon encodings with FP disabled.
> */
> - if (!s->cpacr_fpen) {
> + if (s->fp_excp_el) {
> gen_exception_insn(s, 4, EXCP_UDEF,
> - syn_fp_access_trap(1, 0xe, s->thumb),
> - default_exception_el(s));
> + syn_fp_access_trap(1, 0xe, s->thumb),
> s->fp_excp_el);
> return 0;
> }
>
> @@ -11082,7 +11079,7 @@ static inline void
> gen_intermediate_code_internal(ARMCPU *cpu,
> dc->user = (dc->current_el == 0);
> #endif
> dc->ns = ARM_TBFLAG_NS(tb->flags);
> - dc->cpacr_fpen = ARM_TBFLAG_CPACR_FPEN(tb->flags);
> + dc->fp_excp_el = ARM_TBFLAG_CPACR_FPEN(tb->flags);
> dc->vfp_enabled = ARM_TBFLAG_VFPEN(tb->flags);
> dc->vec_len = ARM_TBFLAG_VECLEN(tb->flags);
> dc->vec_stride = ARM_TBFLAG_VECSTRIDE(tb->flags);
> diff --git a/target-arm/translate.h b/target-arm/translate.h
> index 2eadcb7..bcdcf11 100644
> --- a/target-arm/translate.h
> +++ b/target-arm/translate.h
> @@ -22,7 +22,7 @@ typedef struct DisasContext {
> #endif
> ARMMMUIdx mmu_idx; /* MMU index to use for normal loads/stores */
> bool ns; /* Use non-secure CPREG bank on access */
> - bool cpacr_fpen; /* FP enabled via CPACR.FPEN */
> + int fp_excp_el; /* FP exception EL or 0 if enabled */
> bool el3_is_aa64; /* Flag indicating whether EL3 is AArch64 or not */
> bool vfp_enabled; /* FP enabled via FPSCR.EN */
> int vec_len;
> --
> 1.8.3.2
thanks
-- PMM
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