Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA

[Maciej W. Rozycki]

On Wed, 13 May 2015, Richard Henderson wrote:

> > +static inline void ensure_atomic_msa_block_access(CPUMIPSState *env,
> > +                                                  target_ulong addr,
> > +                                                  int rw,
> > +                                                  int mmu_idx)
> >  {
> > +#if !defined(CONFIG_USER_ONLY)
> > +#define MSA_PAGESPAN(x) (unlikely((((x) & ~TARGET_PAGE_MASK)               
> >  \
> > +                                   + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE))
> > +    CPUState *cs = CPU(mips_env_get_cpu(env));
> > +    target_ulong page_addr;
> >  
> > +    if (MSA_PAGESPAN(addr)) {
> > +        /* first page */
> > +        tlb_fill(cs, addr, rw, mmu_idx, 0);
> > +        /* second page */
> > +        page_addr = (addr & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
> > +        tlb_fill(cs, page_addr, rw, mmu_idx, 0);
> >      }
> > +#endif
> >  }
> 
> This doesn't do quite what you think it does.  It does trap if the page isn't
> mapped at all, but it doesn't trap if e.g. rw is set and the page is 
> read-only.
> That requires a subsequent check for what permissions were installed by
> tlb_set_page.
> 
> I had thought there was a way to look this up besides duplicating the code in
> softmmu_template.h, but I suppose that's in a patch set that never made it in.

 We must have a way to deal with memory access operations issued by a 
single machine instruction crossing a page boundary already as this is 
what MIPS16 SAVE and RESTORE instructions as well as microMIPS SWP, SDP, 
SWM, SDM, LWP, LDP, LWM and LDM ones do.  Perhaps these are worth 
looking into and their approach copying (or reusing) here?

  Maciej