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[Qemu-devel] [PATCH 1/3] tcg: Merge memop and mmu_idx parameters to qemu
|
From: |
Richard Henderson |
|
Subject: |
[Qemu-devel] [PATCH 1/3] tcg: Merge memop and mmu_idx parameters to qemu_ld/st |
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Date: |
Wed, 13 May 2015 12:09:58 -0700 |
At the tcg opcode level, not at the tcg-op.h generator level.
This requires minor changes through all of the tcg backends,
but none of the cpu translators.
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/aarch64/tcg-target.c | 12 ++++++++----
tcg/arm/tcg-target.c | 12 ++++++++----
tcg/i386/tcg-target.c | 12 ++++++++----
tcg/ia64/tcg-target.c | 12 ++++++++----
tcg/mips/tcg-target.c | 12 ++++++++----
tcg/optimize.c | 3 ++-
tcg/ppc/tcg-target.c | 12 ++++++++----
tcg/s390/tcg-target.c | 12 ++++++++----
tcg/sparc/tcg-target.c | 14 +++++++++-----
tcg/tcg-op.c | 22 ++++++++++------------
tcg/tcg-opc.h | 8 ++++----
tcg/tcg.c | 16 +++++++++++-----
tcg/tcg.h | 38 ++++++++++++++++++++++++++++++++++++++
tcg/tci/tcg-target.c | 6 ------
14 files changed, 130 insertions(+), 61 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 87dc245..23b8fda 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1197,9 +1197,11 @@ static void tcg_out_qemu_st_direct(TCGContext *s,
TCGMemOp memop,
}
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOp memop, TCGType ext, int mem_index)
+ TCGMemOpIdx oi, TCGType ext)
{
+ TCGMemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
TCGMemOp s_bits = memop & MO_SIZE;
tcg_insn_unit *label_ptr;
@@ -1214,9 +1216,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg
data_reg, TCGReg addr_reg,
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOp memop, int mem_index)
+ TCGMemOpIdx oi)
{
+ TCGMemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
TCGMemOp s_bits = memop & MO_SIZE;
tcg_insn_unit *label_ptr;
@@ -1515,11 +1519,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, a0, a1, a2, ext, args[3]);
+ tcg_out_qemu_ld(s, a0, a1, a2, ext);
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, REG0(0), a1, a2, args[3]);
+ tcg_out_qemu_st(s, REG0(0), a1, a2);
break;
case INDEX_op_bswap64_i64:
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c
index 01e6fbf..f3221e7 100644
--- a/tcg/arm/tcg-target.c
+++ b/tcg/arm/tcg-target.c
@@ -1463,6 +1463,7 @@ static inline void tcg_out_qemu_ld_direct(TCGContext *s,
TCGMemOp opc,
static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
TCGMemOp opc;
#ifdef CONFIG_SOFTMMU
int mem_index;
@@ -1474,10 +1475,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is64)
datahi = (is64 ? *args++ : 0);
addrlo = *args++;
addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
- opc = *args++;
+ oi = *args++;
+ opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
- mem_index = *args;
+ mem_index = get_mmuidx(oi);
addend = tcg_out_tlb_read(s, addrlo, addrhi, opc & MO_SIZE, mem_index, 1);
/* This a conditional BL only to load a pointer within this opcode into LR
@@ -1592,6 +1594,7 @@ static inline void tcg_out_qemu_st_direct(TCGContext *s,
TCGMemOp opc,
static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is64)
{
TCGReg addrlo, datalo, datahi, addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
TCGMemOp opc;
#ifdef CONFIG_SOFTMMU
int mem_index;
@@ -1603,10 +1606,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is64)
datahi = (is64 ? *args++ : 0);
addrlo = *args++;
addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
- opc = *args++;
+ oi = *args++;
+ opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
- mem_index = *args;
+ mem_index = get_mmuidx(oi);
addend = tcg_out_tlb_read(s, addrlo, addrhi, opc & MO_SIZE, mem_index, 0);
tcg_out_qemu_st_index(s, COND_EQ, opc, datalo, datahi, addrlo, addend);
diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c
index ab63823..a458c8a 100644
--- a/tcg/i386/tcg-target.c
+++ b/tcg/i386/tcg-target.c
@@ -1531,6 +1531,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is64)
{
TCGReg datalo, datahi, addrlo;
TCGReg addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
TCGMemOp opc;
#if defined(CONFIG_SOFTMMU)
int mem_index;
@@ -1542,10 +1543,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is64)
datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
addrlo = *args++;
addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
- opc = *args++;
+ oi = *args++;
+ opc = get_memop(oi);
#if defined(CONFIG_SOFTMMU)
- mem_index = *args++;
+ mem_index = get_mmuidx(oi);
s_bits = opc & MO_SIZE;
tcg_out_tlb_load(s, addrlo, addrhi, mem_index, s_bits,
@@ -1662,6 +1664,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is64)
{
TCGReg datalo, datahi, addrlo;
TCGReg addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
TCGMemOp opc;
#if defined(CONFIG_SOFTMMU)
int mem_index;
@@ -1673,10 +1676,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is64)
datahi = (TCG_TARGET_REG_BITS == 32 && is64 ? *args++ : 0);
addrlo = *args++;
addrhi = (TARGET_LONG_BITS > TCG_TARGET_REG_BITS ? *args++ : 0);
- opc = *args++;
+ oi = *args++;
+ opc = get_memop(oi);
#if defined(CONFIG_SOFTMMU)
- mem_index = *args++;
+ mem_index = get_mmuidx(oi);
s_bits = opc & MO_SIZE;
tcg_out_tlb_load(s, addrlo, addrhi, mem_index, s_bits,
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 25f207d..1920593 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -1634,14 +1634,16 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const
TCGArg *args)
OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1
};
int addr_reg, data_reg, mem_index;
+ TCGMemOpIdx oi;
TCGMemOp opc, s_bits;
uint64_t fin1, fin2;
tcg_insn_unit *label_ptr;
data_reg = args[0];
addr_reg = args[1];
- opc = args[2];
- mem_index = args[3];
+ oi = args[2];
+ opc = get_memop(oi);
+ mem_index = get_mmuidx(oi);
s_bits = opc & MO_SIZE;
/* Read the TLB entry */
@@ -1696,13 +1698,15 @@ static inline void tcg_out_qemu_st(TCGContext *s, const
TCGArg *args)
TCGReg addr_reg, data_reg;
int mem_index;
uint64_t pre1, pre2;
+ TCGMemOpIdx oi;
TCGMemOp opc, s_bits;
tcg_insn_unit *label_ptr;
data_reg = args[0];
addr_reg = args[1];
- opc = args[2];
- mem_index = args[3];
+ oi = args[2];
+ opc = get_memop(oi);
+ mem_index = get_mmuidx(oi);
s_bits = opc & MO_SIZE;
/* Note that we always use LE helper functions, so the bswap insns
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 5414b83..3f86182 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
@@ -1150,6 +1150,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is_64)
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh;
+ TCGMemOpIdx oi;
TCGMemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
@@ -1164,10 +1165,11 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is_64)
data_regh = (is_64 ? *args++ : 0);
addr_regl = *args++;
addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0);
- opc = *args++;
+ oi = *args++;
+ opc = get_memop(oi);
#if defined(CONFIG_SOFTMMU)
- mem_index = *args;
+ mem_index = get_mmuidx(oi);
s_bits = opc & MO_SIZE;
tcg_out_tlb_load(s, base, addr_regl, addr_regh, mem_index,
@@ -1279,6 +1281,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is_64)
{
TCGReg addr_regl, addr_regh __attribute__((unused));
TCGReg data_regl, data_regh, base;
+ TCGMemOpIdx oi;
TCGMemOp opc;
#if defined(CONFIG_SOFTMMU)
tcg_insn_unit *label_ptr[2];
@@ -1290,10 +1293,11 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is_64)
data_regh = (is_64 ? *args++ : 0);
addr_regl = *args++;
addr_regh = (TARGET_LONG_BITS == 64 ? *args++ : 0);
- opc = *args++;
+ oi = *args++;
+ opc = get_memop(oi);
#if defined(CONFIG_SOFTMMU)
- mem_index = *args;
+ mem_index = get_mmuidx(oi);
s_bits = opc & 3;
/* Note that we eliminated the helper's address argument,
diff --git a/tcg/optimize.c b/tcg/optimize.c
index 37c1110..585f1ed 100644
--- a/tcg/optimize.c
+++ b/tcg/optimize.c
@@ -918,7 +918,8 @@ static void tcg_constant_folding(TCGContext *s)
CASE_OP_32_64(qemu_ld):
{
- TCGMemOp mop = args[nb_oargs + nb_iargs];
+ TCGMemOpIdx oi = args[nb_oargs + nb_iargs];
+ TCGMemOp mop = get_memop(oi);
if (!(mop & MO_SIGN)) {
mask = (2ULL << ((8 << (mop & MO_SIZE)) - 1)) - 1;
}
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index 36fd314..b9d02c4 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -1575,6 +1575,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is_64)
{
TCGReg datalo, datahi, addrlo, rbase;
TCGReg addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
TCGMemOp opc, s_bits;
#ifdef CONFIG_SOFTMMU
int mem_index;
@@ -1585,11 +1586,12 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args, bool is_64)
datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
addrlo = *args++;
addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- opc = *args++;
+ oi = *args++;
+ opc = get_memop(oi);
s_bits = opc & MO_SIZE;
#ifdef CONFIG_SOFTMMU
- mem_index = *args;
+ mem_index = get_mmuidx(oi);
addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, true);
/* Load a pointer into the current opcode w/conditional branch-link. */
@@ -1648,6 +1650,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is_64)
{
TCGReg datalo, datahi, addrlo, rbase;
TCGReg addrhi __attribute__((unused));
+ TCGMemOpIdx oi;
TCGMemOp opc, s_bits;
#ifdef CONFIG_SOFTMMU
int mem_index;
@@ -1658,11 +1661,12 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg
*args, bool is_64)
datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0);
addrlo = *args++;
addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0);
- opc = *args++;
+ oi = *args++;
+ opc = get_memop(oi);
s_bits = opc & MO_SIZE;
#ifdef CONFIG_SOFTMMU
- mem_index = *args;
+ mem_index = get_mmuidx(oi);
addrlo = tcg_out_tlb_read(s, s_bits, addrlo, addrhi, mem_index, false);
/* Load a pointer into the current opcode w/conditional branch-link. */
diff --git a/tcg/s390/tcg-target.c b/tcg/s390/tcg-target.c
index be984f5..10577ab 100644
--- a/tcg/s390/tcg-target.c
+++ b/tcg/s390/tcg-target.c
@@ -1632,9 +1632,11 @@ static void tcg_prepare_user_ldst(TCGContext *s, TCGReg
*addr_reg,
#endif /* CONFIG_SOFTMMU */
static void tcg_out_qemu_ld(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOp opc, int mem_index)
+ TCGMemOpIdx oi)
{
+ TCGMemOp opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
TCGReg base_reg;
@@ -1657,9 +1659,11 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg
data_reg, TCGReg addr_reg,
}
static void tcg_out_qemu_st(TCGContext* s, TCGReg data_reg, TCGReg addr_reg,
- TCGMemOp opc, int mem_index)
+ TCGMemOpIdx oi)
{
+ TCGMemOp opc = get_memop(oi);
#ifdef CONFIG_SOFTMMU
+ unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
TCGReg base_reg;
@@ -1920,11 +1924,11 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode
opc,
case INDEX_op_qemu_ld_i32:
/* ??? Technically we can use a non-extending instruction. */
case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3]);
+ tcg_out_qemu_ld(s, args[0], args[1], args[2]);
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args[0], args[1], args[2], args[3]);
+ tcg_out_qemu_st(s, args[0], args[1], args[2]);
break;
case INDEX_op_ld16s_i64:
diff --git a/tcg/sparc/tcg-target.c b/tcg/sparc/tcg-target.c
index f9b616f..ccc3173 100644
--- a/tcg/sparc/tcg-target.c
+++ b/tcg/sparc/tcg-target.c
@@ -1070,9 +1070,11 @@ static const int qemu_st_opc[16] = {
};
static void tcg_out_qemu_ld(TCGContext *s, TCGReg data, TCGReg addr,
- TCGMemOp memop, int memi, bool is_64)
+ TCGMemOpIdx oi, bool is_64)
{
+ TCGMemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
+ unsigned memi = get_mmuidx(oi);
TCGMemOp s_bits = memop & MO_SIZE;
TCGReg addrz, param;
tcg_insn_unit *func;
@@ -1150,9 +1152,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg data,
TCGReg addr,
}
static void tcg_out_qemu_st(TCGContext *s, TCGReg data, TCGReg addr,
- TCGMemOp memop, int memi)
+ TCGMemOpIdx oi)
{
+ TCGMemOp memop = get_memop(oi);
#ifdef CONFIG_SOFTMMU
+ unsigned memi = get_mmuidx(oi);
TCGMemOp s_bits = memop & MO_SIZE;
TCGReg addrz, param;
tcg_insn_unit *func;
@@ -1363,14 +1367,14 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, a0, a1, a2, args[3], false);
+ tcg_out_qemu_ld(s, a0, a1, a2, false);
break;
case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, a0, a1, a2, args[3], true);
+ tcg_out_qemu_ld(s, a0, a1, a2, true);
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, a0, a1, a2, args[3]);
+ tcg_out_qemu_st(s, a0, a1, a2);
break;
case INDEX_op_ld32s_i64:
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 2b6be75..45098c3 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg-op.c
@@ -1873,15 +1873,14 @@ static inline TCGMemOp tcg_canonicalize_memop(TCGMemOp
op, bool is64, bool st)
static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val, TCGv addr,
TCGMemOp memop, TCGArg idx)
{
+ TCGMemOpIdx oi = make_memop_idx(memop, idx);
#if TARGET_LONG_BITS == 32
- tcg_gen_op4ii_i32(opc, val, addr, memop, idx);
+ tcg_gen_op3i_i32(opc, val, addr, oi);
#else
if (TCG_TARGET_REG_BITS == 32) {
- tcg_gen_op5ii_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr),
- memop, idx);
+ tcg_gen_op4i_i32(opc, val, TCGV_LOW(addr), TCGV_HIGH(addr), oi);
} else {
- tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr),
- memop, idx);
+ tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_I64(addr), oi);
}
#endif
}
@@ -1889,20 +1888,19 @@ static void gen_ldst_i32(TCGOpcode opc, TCGv_i32 val,
TCGv addr,
static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 val, TCGv addr,
TCGMemOp memop, TCGArg idx)
{
+ TCGMemOpIdx oi = make_memop_idx(memop, idx);
#if TARGET_LONG_BITS == 32
if (TCG_TARGET_REG_BITS == 32) {
- tcg_gen_op5ii_i32(opc, TCGV_LOW(val), TCGV_HIGH(val),
- addr, memop, idx);
+ tcg_gen_op4i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val), addr, oi);
} else {
- tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr),
- memop, idx);
+ tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_I32(addr), oi);
}
#else
if (TCG_TARGET_REG_BITS == 32) {
- tcg_gen_op6ii_i32(opc, TCGV_LOW(val), TCGV_HIGH(val),
- TCGV_LOW(addr), TCGV_HIGH(addr), memop, idx);
+ tcg_gen_op5i_i32(opc, TCGV_LOW(val), TCGV_HIGH(val),
+ TCGV_LOW(addr), TCGV_HIGH(addr), oi);
} else {
- tcg_gen_op4ii_i64(opc, val, addr, memop, idx);
+ tcg_gen_op3i_i64(opc, val, addr, oi);
}
#endif
}
diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h
index 42d0cfe..13ccb60 100644
--- a/tcg/tcg-opc.h
+++ b/tcg/tcg-opc.h
@@ -179,13 +179,13 @@ DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END)
#define TLADDR_ARGS (TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? 1 : 2)
#define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2)
-DEF(qemu_ld_i32, 1, TLADDR_ARGS, 2,
+DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
-DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 2,
+DEF(qemu_st_i32, 0, TLADDR_ARGS + 1, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS)
-DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 2,
+DEF(qemu_ld_i64, DATA64_ARGS, TLADDR_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
-DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 2,
+DEF(qemu_st_i64, 0, TLADDR_ARGS + DATA64_ARGS, 1,
TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS | TCG_OPF_64BIT)
#undef TLADDR_ARGS
diff --git a/tcg/tcg.c b/tcg/tcg.c
index f1558b7..8b43bbb 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1071,12 +1071,18 @@ void tcg_dump_ops(TCGContext *s)
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_ld_i64:
case INDEX_op_qemu_st_i64:
- if (args[k] < ARRAY_SIZE(ldst_name) && ldst_name[args[k]]) {
- qemu_log(",%s", ldst_name[args[k++]]);
- } else {
- qemu_log(",$0x%" TCG_PRIlx, args[k++]);
+ {
+ TCGMemOpIdx oi = args[k++];
+ TCGMemOp op = get_memop(oi);
+ unsigned ix = get_mmuidx(oi);
+
+ if (op < ARRAY_SIZE(ldst_name) && ldst_name[op]) {
+ qemu_log(",%s,%u", ldst_name[op], ix);
+ } else {
+ qemu_log(",$0x%x,%u", op, ix);
+ }
+ i = 1;
}
- i = 1;
break;
default:
i = 0;
diff --git a/tcg/tcg.h b/tcg/tcg.h
index fbb3daf..99d3f14 100644
--- a/tcg/tcg.h
+++ b/tcg/tcg.h
@@ -826,6 +826,44 @@ static inline size_t tcg_current_code_size(TCGContext *s)
return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
}
+/* Combine the TCGMemOp and mmu_idx parameters into a single value. */
+typedef uint32_t TCGMemOpIdx;
+
+/**
+ * make_memop_idx
+ * @op: memory operation
+ * @idx: mmu index
+ *
+ * Encode these values into a single parameter.
+ */
+static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
+{
+ tcg_debug_assert(idx <= 15);
+ return (op << 4) | idx;
+}
+
+/**
+ * get_memop
+ * @oi: combined op/idx parameter
+ *
+ * Extract the memory operation from the combined value.
+ */
+static inline TCGMemOp get_memop(TCGMemOpIdx oi)
+{
+ return oi >> 4;
+}
+
+/**
+ * get_mmuidx
+ * @oi: combined op/idx parameter
+ *
+ * Extract the mmu index from the combined value.
+ */
+static inline unsigned get_mmuidx(TCGMemOpIdx oi)
+{
+ return oi & 15;
+}
+
/**
* tcg_qemu_tb_exec:
* @env: CPUArchState * for the CPU
diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c
index fb2339d..10affab 100644
--- a/tcg/tci/tcg-target.c
+++ b/tcg/tci/tcg-target.c
@@ -763,9 +763,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
tcg_out_r(s, *args++);
}
tcg_out_i(s, *args++);
-#ifdef CONFIG_SOFTMMU
- tcg_out_i(s, *args);
-#endif
break;
case INDEX_op_qemu_ld_i64:
tcg_out_r(s, *args++);
@@ -777,9 +774,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const
TCGArg *args,
tcg_out_r(s, *args++);
}
tcg_out_i(s, *args++);
-#ifdef CONFIG_SOFTMMU
- tcg_out_i(s, *args);
-#endif
break;
case INDEX_op_qemu_st_i32:
tcg_out_r(s, *args++);
--
2.1.0
[Qemu-devel] [PATCH 2/3] tcg: Push merged memop+mmu_idx parameter to softmmu routines, Richard Henderson, 2015/05/13